Elli Peselev
Examiner (ID: 14966)
Most Active Art Unit | 1623 |
Art Unit(s) | 1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802 |
Total Applications | 2819 |
Issued Applications | 1823 |
Pending Applications | 143 |
Abandoned Applications | 853 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 10854276
[patent_doc_number] => 08880987
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-04
[patent_title] => 'Checksum using sums of permutation sub-matrices'
[patent_app_type] => utility
[patent_app_number] => 13/558846
[patent_app_country] => US
[patent_app_date] => 2012-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 12541
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558846
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/558846 | Checksum using sums of permutation sub-matrices | Jul 25, 2012 | Issued |
Array
(
[id] => 9680603
[patent_doc_number] => 08819531
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-26
[patent_title] => 'Systems and methods for information divergence based data processing'
[patent_app_type] => utility
[patent_app_number] => 13/558245
[patent_app_country] => US
[patent_app_date] => 2012-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 10998
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558245
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/558245 | Systems and methods for information divergence based data processing | Jul 24, 2012 | Issued |
Array
(
[id] => 9781392
[patent_doc_number] => 08856616
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-07
[patent_title] => 'Two dimensional encoding for non-volatile memory blocks'
[patent_app_type] => utility
[patent_app_number] => 13/556088
[patent_app_country] => US
[patent_app_date] => 2012-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2774
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13556088
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/556088 | Two dimensional encoding for non-volatile memory blocks | Jul 22, 2012 | Issued |
Array
(
[id] => 8488368
[patent_doc_number] => 20120287775
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-15
[patent_title] => 'AUTOMATIC RETRANSMISSION REQUEST CONTROL SYSTEM AND RETRANSMISSION METHOD IN MIMO-OFDM SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 13/554748
[patent_app_country] => US
[patent_app_date] => 2012-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3475
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13554748
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/554748 | Automatic retransmission request control system and retransmission method in mimo-OFDM system | Jul 19, 2012 | Issued |
Array
(
[id] => 9765936
[patent_doc_number] => 08850284
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-30
[patent_title] => 'Flash memory controller and data reading method'
[patent_app_type] => utility
[patent_app_number] => 13/552651
[patent_app_country] => US
[patent_app_date] => 2012-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4460
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13552651
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/552651 | Flash memory controller and data reading method | Jul 18, 2012 | Issued |
Array
(
[id] => 9271093
[patent_doc_number] => 20140026011
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-23
[patent_title] => 'Memory with Dynamic Error Detection and Correction'
[patent_app_type] => utility
[patent_app_number] => 13/551485
[patent_app_country] => US
[patent_app_date] => 2012-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4342
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13551485
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/551485 | Memory with dynamic error detection and correction | Jul 16, 2012 | Issued |
Array
(
[id] => 9271086
[patent_doc_number] => 20140026004
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-23
[patent_title] => 'Systems and Methods for Defect Scanning'
[patent_app_type] => utility
[patent_app_number] => 13/551523
[patent_app_country] => US
[patent_app_date] => 2012-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6944
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13551523
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/551523 | Systems and methods for defect scanning | Jul 16, 2012 | Issued |
Array
(
[id] => 9707434
[patent_doc_number] => 08832529
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-09
[patent_title] => 'Device and method for testing a memory of an electric tool'
[patent_app_type] => utility
[patent_app_number] => 13/550056
[patent_app_country] => US
[patent_app_date] => 2012-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2766
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13550056
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/550056 | Device and method for testing a memory of an electric tool | Jul 15, 2012 | Issued |
Array
(
[id] => 8716193
[patent_doc_number] => 08402345
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-03-19
[patent_title] => 'Methods and apparatus for providing multilevel coset coding and probabilistic error correction'
[patent_app_type] => utility
[patent_app_number] => 13/548409
[patent_app_country] => US
[patent_app_date] => 2012-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7823
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13548409
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/548409 | Methods and apparatus for providing multilevel coset coding and probabilistic error correction | Jul 12, 2012 | Issued |
Array
(
[id] => 9680584
[patent_doc_number] => 08819511
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-26
[patent_title] => 'Methods and systems for an automated test configuration to identify logic device defects'
[patent_app_type] => utility
[patent_app_number] => 13/546793
[patent_app_country] => US
[patent_app_date] => 2012-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4954
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13546793
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/546793 | Methods and systems for an automated test configuration to identify logic device defects | Jul 10, 2012 | Issued |
Array
(
[id] => 9707420
[patent_doc_number] => 08832515
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-09
[patent_title] => 'Block acknowledgement mechanism including sequence number acknowledgement and retry bit'
[patent_app_type] => utility
[patent_app_number] => 13/545933
[patent_app_country] => US
[patent_app_date] => 2012-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6937
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13545933
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/545933 | Block acknowledgement mechanism including sequence number acknowledgement and retry bit | Jul 9, 2012 | Issued |
Array
(
[id] => 10860797
[patent_doc_number] => 08887015
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-11
[patent_title] => 'Apparatus and method for designing semiconductor device, and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/544491
[patent_app_country] => US
[patent_app_date] => 2012-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 25
[patent_no_of_words] => 12793
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13544491
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/544491 | Apparatus and method for designing semiconductor device, and semiconductor device | Jul 8, 2012 | Issued |
Array
(
[id] => 9665926
[patent_doc_number] => 08812936
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-19
[patent_title] => 'Using slow response memory device on a fast response interface'
[patent_app_type] => utility
[patent_app_number] => 13/542958
[patent_app_country] => US
[patent_app_date] => 2012-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 6906
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13542958
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/542958 | Using slow response memory device on a fast response interface | Jul 5, 2012 | Issued |
Array
(
[id] => 9623350
[patent_doc_number] => 08793545
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-29
[patent_title] => 'Apparatus and method for clock glitch detection during at-speed testing'
[patent_app_type] => utility
[patent_app_number] => 13/540670
[patent_app_country] => US
[patent_app_date] => 2012-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3756
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13540670
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/540670 | Apparatus and method for clock glitch detection during at-speed testing | Jul 2, 2012 | Issued |
Array
(
[id] => 9207730
[patent_doc_number] => 20140006907
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-02
[patent_title] => 'METHODS AND ARRANGEMENTS FOR ERROR CORRECTION IN DECODING DATA FROM AN ELECTROMAGNETIC RADIATOR'
[patent_app_type] => utility
[patent_app_number] => 13/539354
[patent_app_country] => US
[patent_app_date] => 2012-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 12917
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13539354
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/539354 | Methods and arrangements for error correction in decoding data from an electromagnetic radiator | Jun 29, 2012 | Issued |
Array
(
[id] => 9207708
[patent_doc_number] => 20140006885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-02
[patent_title] => 'MEMORY ARCHITECTURE AND ASSOCIATED SERIAL DIRECT ACCESS CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/536139
[patent_app_country] => US
[patent_app_date] => 2012-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4893
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13536139
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/536139 | Memory architecture and associated serial direct access circuit | Jun 27, 2012 | Issued |
Array
(
[id] => 9665931
[patent_doc_number] => 08812941
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-19
[patent_title] => 'Viterbi device and method using a posteriori information'
[patent_app_type] => utility
[patent_app_number] => 13/536041
[patent_app_country] => US
[patent_app_date] => 2012-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2579
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13536041
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/536041 | Viterbi device and method using a posteriori information | Jun 27, 2012 | Issued |
Array
(
[id] => 9680592
[patent_doc_number] => 08819519
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-26
[patent_title] => 'Systems and methods for enhanced accuracy NPML calibration'
[patent_app_type] => utility
[patent_app_number] => 13/535799
[patent_app_country] => US
[patent_app_date] => 2012-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 8826
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535799
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/535799 | Systems and methods for enhanced accuracy NPML calibration | Jun 27, 2012 | Issued |
Array
(
[id] => 8985216
[patent_doc_number] => 08516346
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-20
[patent_title] => 'Packet transmission apparatus, communication system and program'
[patent_app_type] => utility
[patent_app_number] => 13/532300
[patent_app_country] => US
[patent_app_date] => 2012-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6643
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13532300
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/532300 | Packet transmission apparatus, communication system and program | Jun 24, 2012 | Issued |
Array
(
[id] => 9164391
[patent_doc_number] => RE044614
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2013-11-26
[patent_title] => 'Reliability unit for determining a reliability value for at least one bit decision'
[patent_app_type] => reissue
[patent_app_number] => 13/530573
[patent_app_country] => US
[patent_app_date] => 2012-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 7620
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13530573
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/530573 | Reliability unit for determining a reliability value for at least one bit decision | Jun 21, 2012 | Issued |