Elli Peselev
Examiner (ID: 14966)
Most Active Art Unit | 1623 |
Art Unit(s) | 1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802 |
Total Applications | 2819 |
Issued Applications | 1823 |
Pending Applications | 143 |
Abandoned Applications | 853 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
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[id] => 9652280
[patent_doc_number] => 08806317
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-12
[patent_title] => 'Method for coding and decoding digital data, particularly data processed in a microprocessor unit'
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[patent_app_number] => 13/379363
[patent_app_country] => US
[patent_app_date] => 2010-06-22
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Array
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[patent_doc_number] => 20100313091
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[patent_kind] => A1
[patent_issue_date] => 2010-12-09
[patent_title] => 'APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/794183
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Array
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[id] => 8799547
[patent_doc_number] => 08438436
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[patent_issue_date] => 2013-05-07
[patent_title] => 'Secure design-for-test scan chains'
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[patent_app_number] => 12/794221
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Array
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[patent_doc_number] => 08407545
[patent_country] => US
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[patent_issue_date] => 2013-03-26
[patent_title] => 'Communication device'
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[patent_issue_date] => 2013-05-21
[patent_title] => 'Memory system and control method for the same'
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Array
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[patent_issue_date] => 2013-02-12
[patent_title] => 'Electronic storage device and control method thereof'
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Array
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[patent_title] => 'SCAN TEST CIRCUIT, AND METHOD AND PROGRAM FOR DESIGNING SAME'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/789594 | Scan test circuit, and method and program for designing same | May 27, 2010 | Issued |
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[patent_title] => 'Methods and devices to reduce outer code failure rate variability'
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Array
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[id] => 7512785
[patent_doc_number] => 20110258495
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[patent_issue_date] => 2011-10-20
[patent_title] => 'METHODS OF CALCULATING COMPENSATION VOLTAGE AND ADJUSTING THRESHOLD VOLTAGE AND MEMORY APPARATUS AND CONTROLLER'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/788649 | Methods of calculating compensation voltage and adjusting threshold voltage and memory apparatus and controller | May 26, 2010 | Issued |
Array
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[patent_title] => 'Self-adjusting critical path timing of multi-core VLSI chip'
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Array
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[patent_title] => 'NON-VOLATILE MEMORY DEVICE AND DATA PROCESSING METHOD THEREOF'
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Array
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Array
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Array
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Array
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