Search

Elli Peselev

Examiner (ID: 14966)

Most Active Art Unit
1623
Art Unit(s)
1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802
Total Applications
2819
Issued Applications
1823
Pending Applications
143
Abandoned Applications
853

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16373522 [patent_doc_number] => 10805300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Computer network cross-boundary protection [patent_app_type] => utility [patent_app_number] => 16/041867 [patent_app_country] => US [patent_app_date] => 2018-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2801 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16041867 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/041867
Computer network cross-boundary protection Jul 22, 2018 Issued
Array ( [id] => 15885385 [patent_doc_number] => 10649029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => TCKC/TMSC counter, gating circuitry for selection, deselection, technology specific outputs [patent_app_type] => utility [patent_app_number] => 16/038939 [patent_app_country] => US [patent_app_date] => 2018-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7568 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16038939 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/038939
TCKC/TMSC counter, gating circuitry for selection, deselection, technology specific outputs Jul 17, 2018 Issued
Array ( [id] => 16147747 [patent_doc_number] => 10706948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Multi-level memory safety of a sensor integrated circuit [patent_app_type] => utility [patent_app_number] => 16/033722 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6843 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033722 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033722
Multi-level memory safety of a sensor integrated circuit Jul 11, 2018 Issued
Array ( [id] => 15856881 [patent_doc_number] => 10643735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => Passive array test structure for cross-point memory characterization [patent_app_type] => utility [patent_app_number] => 16/033156 [patent_app_country] => US [patent_app_date] => 2018-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4898 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16033156 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/033156
Passive array test structure for cross-point memory characterization Jul 10, 2018 Issued
Array ( [id] => 16044915 [patent_doc_number] => 10684326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Method and device for testing a chain of flip-flops [patent_app_type] => utility [patent_app_number] => 16/031395 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3181 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16031395 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/031395
Method and device for testing a chain of flip-flops Jul 9, 2018 Issued
Array ( [id] => 14475183 [patent_doc_number] => 20190189238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => Method, Apparatus and Electronic Device For Read/Write Speed Testing [patent_app_type] => utility [patent_app_number] => 16/031842 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16031842 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/031842
Method, apparatus and electronic device for read/write speed testing Jul 9, 2018 Issued
Array ( [id] => 14511637 [patent_doc_number] => 20190199473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => Decoding Signals By Guessing Noise [patent_app_type] => utility [patent_app_number] => 16/026811 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026811 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/026811
Decoding concatenated codes by guessing noise Jul 2, 2018 Issued
Array ( [id] => 14511445 [patent_doc_number] => 20190199377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => Decoding Signals Codes by Guessing Noise [patent_app_type] => utility [patent_app_number] => 16/026822 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026822 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/026822
Decoding signals by guessing noise Jul 2, 2018 Issued
Array ( [id] => 16065179 [patent_doc_number] => 10691539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Grown defect detection and mitigation using ECC in memory systems [patent_app_type] => utility [patent_app_number] => 16/022199 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 34687 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022199
Grown defect detection and mitigation using ECC in memory systems Jun 27, 2018 Issued
Array ( [id] => 15875241 [patent_doc_number] => 20200145024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => CODE BLOCK SEGMENTATION METHOD, TERMINAL, BASE STATION, AND COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/630831 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16630831 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/630831
Code block segmentation method, terminal, base station, and computer-readable storage medium Jun 27, 2018 Issued
Array ( [id] => 15854799 [patent_doc_number] => 10642684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => Memory command interleaving [patent_app_type] => utility [patent_app_number] => 16/022276 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022276
Memory command interleaving Jun 27, 2018 Issued
Array ( [id] => 16200698 [patent_doc_number] => 10725861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Error correction code memory security [patent_app_type] => utility [patent_app_number] => 16/022447 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9302 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022447
Error correction code memory security Jun 27, 2018 Issued
Array ( [id] => 16186060 [patent_doc_number] => 10719392 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-21 [patent_title] => Selective sampling for data recovery [patent_app_type] => utility [patent_app_number] => 16/020013 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16020013 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/020013
Selective sampling for data recovery Jun 26, 2018 Issued
Array ( [id] => 13483197 [patent_doc_number] => 20180293141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => HANDLING FAILING MEMORY DEVICES IN A DISPERSED STORAGE NETWORK [patent_app_type] => utility [patent_app_number] => 16/001671 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001671 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001671
Handling failing memory devices in a dispersed storage network Jun 5, 2018 Issued
Array ( [id] => 13436719 [patent_doc_number] => 20180269902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => SYSTEM AND METHOD FOR DYNAMIC SCALING OF LDPC DECODER IN A SOLID STATE DRIVE [patent_app_type] => utility [patent_app_number] => 15/984179 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15984179 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/984179
System and method for dynamic scaling of LDPC decoder in a solid state drive May 17, 2018 Issued
Array ( [id] => 15901317 [patent_doc_number] => 20200150177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => INTEGRATED CIRCUIT TEST APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 16/614395 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16614395 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/614395
Integrated circuit test apparatus and method May 16, 2018 Issued
Array ( [id] => 16278938 [patent_doc_number] => 10761969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Nonvolatile memory device and operation method thereof [patent_app_type] => utility [patent_app_number] => 15/981443 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 10961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981443 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981443
Nonvolatile memory device and operation method thereof May 15, 2018 Issued
Array ( [id] => 16133861 [patent_doc_number] => 10700709 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-30 [patent_title] => Linear block code decoding [patent_app_type] => utility [patent_app_number] => 15/965271 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15965271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/965271
Linear block code decoding Apr 26, 2018 Issued
Array ( [id] => 14605039 [patent_doc_number] => 10355719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-16 [patent_title] => System and method for informational reduction [patent_app_type] => utility [patent_app_number] => 15/955354 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15955354 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/955354
System and method for informational reduction Apr 16, 2018 Issued
Array ( [id] => 13361469 [patent_doc_number] => 20180232274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => GLOBAL ERROR RECOVERY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/954535 [patent_app_country] => US [patent_app_date] => 2018-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15954535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/954535
Global error recovery system Apr 15, 2018 Issued
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