Search

Ellis B. Ramirez

Examiner (ID: 10250)

Most Active Art Unit
2304
Art Unit(s)
2899, 2304, 3658, 3661, 2756, 2414, 2757, 2314
Total Applications
1087
Issued Applications
840
Pending Applications
138
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2965559 [patent_doc_number] => 05243541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-07 [patent_title] => 'Imaging lidar system for shallow and coastal water' [patent_app_type] => 1 [patent_app_number] => 7/919346 [patent_app_country] => US [patent_app_date] => 1992-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5747 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/243/05243541.pdf [firstpage_image] =>[orig_patent_app_number] => 919346 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/919346
Imaging lidar system for shallow and coastal water Jul 22, 1992 Issued
Array ( [id] => 2985910 [patent_doc_number] => 05225998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Quality control using multi-process performance analysis' [patent_app_type] => 1 [patent_app_number] => 7/912083 [patent_app_country] => US [patent_app_date] => 1992-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8338 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/225/05225998.pdf [firstpage_image] =>[orig_patent_app_number] => 912083 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/912083
Quality control using multi-process performance analysis Jul 8, 1992 Issued
Array ( [id] => 3574050 [patent_doc_number] => 05483470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Timing verification by successive approximation' [patent_app_type] => 1 [patent_app_number] => 7/906082 [patent_app_country] => US [patent_app_date] => 1992-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 16351 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/483/05483470.pdf [firstpage_image] =>[orig_patent_app_number] => 906082 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/906082
Timing verification by successive approximation Jun 28, 1992 Issued
Array ( [id] => 3435980 [patent_doc_number] => 05404359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Fail safe, fault tolerant circuit for manufacturing test logic on application specific integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/906196 [patent_app_country] => US [patent_app_date] => 1992-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 7610 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404359.pdf [firstpage_image] =>[orig_patent_app_number] => 906196 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/906196
Fail safe, fault tolerant circuit for manufacturing test logic on application specific integrated circuits Jun 28, 1992 Issued
Array ( [id] => 3421149 [patent_doc_number] => 05412582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-02 [patent_title] => 'Surveillance system' [patent_app_type] => 1 [patent_app_number] => 7/905366 [patent_app_country] => US [patent_app_date] => 1992-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2822 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/412/05412582.pdf [firstpage_image] =>[orig_patent_app_number] => 905366 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/905366
Surveillance system Jun 28, 1992 Issued
07/903574 GENERALIZED SOLIDS MODELING FOR THREE-DIMENSIONAL TOPOGRAPHY SIMULATION Jun 23, 1992 Abandoned
Array ( [id] => 3436879 [patent_doc_number] => 05455778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Bearing design analysis apparatus and method' [patent_app_type] => 1 [patent_app_number] => 7/902811 [patent_app_country] => US [patent_app_date] => 1992-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 141 [patent_no_of_words] => 36804 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455778.pdf [firstpage_image] =>[orig_patent_app_number] => 902811 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/902811
Bearing design analysis apparatus and method Jun 22, 1992 Issued
07/898827 AUDIO COMMUNICATION SYSTEM FOR A COMPUTER NETWORK Jun 14, 1992 Abandoned
07/892626 PROCESS AND SYSTEM FOR MEASURING THE TEMPORAL COURSE OF A PERIODIC SIGNAL HAVING HIGH TIME RESOLUTION ACCORDING TO A BOXCAR-LIKE PROCESS Jun 1, 1992 Abandoned
Array ( [id] => 3106271 [patent_doc_number] => 05293374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Measurement system control using real-time clocks and data buffers' [patent_app_type] => 1 [patent_app_number] => 7/887591 [patent_app_country] => US [patent_app_date] => 1992-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3003 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293374.pdf [firstpage_image] =>[orig_patent_app_number] => 887591 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/887591
Measurement system control using real-time clocks and data buffers May 19, 1992 Issued
Array ( [id] => 3497372 [patent_doc_number] => 05475624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Test generation by environment emulation' [patent_app_type] => 1 [patent_app_number] => 7/876566 [patent_app_country] => US [patent_app_date] => 1992-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 9930 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475624.pdf [firstpage_image] =>[orig_patent_app_number] => 876566 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/876566
Test generation by environment emulation Apr 29, 1992 Issued
07/867052 DIGITAL AUDIO WORKSTATION PROVIDING DIGITAL STORAGE AND DISPLAY OF VIDEO INFORMATION Apr 9, 1992 Abandoned
Array ( [id] => 3039198 [patent_doc_number] => 05349542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Method for sizing widths of power busses in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/862095 [patent_app_country] => US [patent_app_date] => 1992-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4008 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349542.pdf [firstpage_image] =>[orig_patent_app_number] => 862095 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/862095
Method for sizing widths of power busses in integrated circuits Apr 1, 1992 Issued
Array ( [id] => 3500551 [patent_doc_number] => 05440568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'System for determining the operations of an integrated circuit and processor for use therein' [patent_app_type] => 1 [patent_app_number] => 7/859578 [patent_app_country] => US [patent_app_date] => 1992-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3042 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440568.pdf [firstpage_image] =>[orig_patent_app_number] => 859578 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/859578
System for determining the operations of an integrated circuit and processor for use therein Mar 26, 1992 Issued
Array ( [id] => 3783585 [patent_doc_number] => 05774381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Modeling and simulation of catalytic cracking' [patent_app_type] => 1 [patent_app_number] => 7/845971 [patent_app_country] => US [patent_app_date] => 1992-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7386 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774381.pdf [firstpage_image] =>[orig_patent_app_number] => 845971 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/845971
Modeling and simulation of catalytic cracking Mar 3, 1992 Issued
Array ( [id] => 3083856 [patent_doc_number] => 05365459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-15 [patent_title] => 'Continuous stack flow rate monitor' [patent_app_type] => 1 [patent_app_number] => 7/840529 [patent_app_country] => US [patent_app_date] => 1992-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1415 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/365/05365459.pdf [firstpage_image] =>[orig_patent_app_number] => 840529 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/840529
Continuous stack flow rate monitor Feb 24, 1992 Issued
07/839182 PROGRAMMABLE ELECTRICAL ENERGY METER AND METHODS THEREFORE Feb 20, 1992 Abandoned
Array ( [id] => 3083798 [patent_doc_number] => 05365456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-15 [patent_title] => 'Method for modelling the electron density of a crystal' [patent_app_type] => 1 [patent_app_number] => 7/831258 [patent_app_country] => US [patent_app_date] => 1992-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 11397 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/365/05365456.pdf [firstpage_image] =>[orig_patent_app_number] => 831258 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/831258
Method for modelling the electron density of a crystal Jan 29, 1992 Issued
07/824341 APPARATUS AND METHOD FOR EMULATION OF ELECTRONIC HARDWARE SYSTEMS Jan 22, 1992 Abandoned
Array ( [id] => 3008688 [patent_doc_number] => 05359534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Verification method of logical circuit layout patterns' [patent_app_type] => 1 [patent_app_number] => 7/823966 [patent_app_country] => US [patent_app_date] => 1992-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1357 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359534.pdf [firstpage_image] =>[orig_patent_app_number] => 823966 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/823966
Verification method of logical circuit layout patterns Jan 21, 1992 Issued
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