Elly Gerald Stoica
Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )
Most Active Art Unit | 1647 |
Art Unit(s) | 1647, 1646 |
Total Applications | 1381 |
Issued Applications | 805 |
Pending Applications | 99 |
Abandoned Applications | 477 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 10172723
[patent_doc_number] => 09203440
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-12-01
[patent_title] => 'Matrix expansion'
[patent_app_type] => utility
[patent_app_number] => 13/752718
[patent_app_country] => US
[patent_app_date] => 2013-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 105
[patent_figures_cnt] => 107
[patent_no_of_words] => 14653
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13752718
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/752718 | Matrix expansion | Jan 28, 2013 | Issued |
Array
(
[id] => 9056920
[patent_doc_number] => 20130254634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'UNIVERSAL OBJECT DELIVERY AND TEMPLATE-BASED FILE DELIVERY'
[patent_app_type] => utility
[patent_app_number] => 13/753442
[patent_app_country] => US
[patent_app_date] => 2013-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 15596
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753442
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/753442 | Universal object delivery and template-based file delivery | Jan 28, 2013 | Issued |
Array
(
[id] => 10086095
[patent_doc_number] => 09123445
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-01
[patent_title] => 'Storage control system with data management mechanism and method of operation thereof'
[patent_app_type] => utility
[patent_app_number] => 13/746542
[patent_app_country] => US
[patent_app_date] => 2013-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 10251
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13746542
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/746542 | Storage control system with data management mechanism and method of operation thereof | Jan 21, 2013 | Issued |
Array
(
[id] => 9012503
[patent_doc_number] => 08527824
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-03
[patent_title] => 'Testing of multi-clock domains'
[patent_app_type] => utility
[patent_app_number] => 13/739799
[patent_app_country] => US
[patent_app_date] => 2013-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6370
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739799
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/739799 | Testing of multi-clock domains | Jan 10, 2013 | Issued |
Array
(
[id] => 9563904
[patent_doc_number] => 20140181617
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-26
[patent_title] => 'MANAGEMENT OF NON-VALID DECISION PATTERNS OF A SOFT READ RETRY OPERATION'
[patent_app_type] => utility
[patent_app_number] => 13/721739
[patent_app_country] => US
[patent_app_date] => 2012-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3067
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721739
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/721739 | Management of non-valid decision patterns of a soft read retry operation | Dec 19, 2012 | Issued |
Array
(
[id] => 10124283
[patent_doc_number] => 09158642
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-13
[patent_title] => 'Method of testing multiple data packet signal transceivers concurrently'
[patent_app_type] => utility
[patent_app_number] => 13/721210
[patent_app_country] => US
[patent_app_date] => 2012-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3614
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721210
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/721210 | Method of testing multiple data packet signal transceivers concurrently | Dec 19, 2012 | Issued |
Array
(
[id] => 9563912
[patent_doc_number] => 20140181625
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-26
[patent_title] => 'READ CHANNEL DATA SIGNAL DETECTION WITH REDUCED-STATE TRELLIS'
[patent_app_type] => utility
[patent_app_number] => 13/721417
[patent_app_country] => US
[patent_app_date] => 2012-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4160
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721417
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/721417 | READ CHANNEL DATA SIGNAL DETECTION WITH REDUCED-STATE TRELLIS | Dec 19, 2012 | Abandoned |
Array
(
[id] => 8906470
[patent_doc_number] => 20130173973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-04
[patent_title] => 'DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/720332
[patent_app_country] => US
[patent_app_date] => 2012-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 15269
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13720332
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/720332 | DEVICE | Dec 18, 2012 | Abandoned |
Array
(
[id] => 9548730
[patent_doc_number] => 20140173378
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-19
[patent_title] => 'PARITY DATA MANAGEMENT FOR A MEMORY ARCHITECTURE'
[patent_app_type] => utility
[patent_app_number] => 13/720504
[patent_app_country] => US
[patent_app_date] => 2012-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6082
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13720504
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/720504 | Parity data management for a memory architecture | Dec 18, 2012 | Issued |
Array
(
[id] => 9623346
[patent_doc_number] => 08793541
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-29
[patent_title] => 'Link equalization tester'
[patent_app_type] => utility
[patent_app_number] => 13/719350
[patent_app_country] => US
[patent_app_date] => 2012-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7174
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719350
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/719350 | Link equalization tester | Dec 18, 2012 | Issued |
Array
(
[id] => 9548740
[patent_doc_number] => 20140173386
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-19
[patent_title] => 'Circuitry and Method for Correcting 3-bit Errors Containing Adjacent 2-Bit Error'
[patent_app_type] => utility
[patent_app_number] => 13/720780
[patent_app_country] => US
[patent_app_date] => 2012-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 18541
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13720780
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/720780 | Circuitry and method for correcting 3-bit errors containing adjacent 2-bit error | Dec 18, 2012 | Issued |
Array
(
[id] => 9871621
[patent_doc_number] => 08959413
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-02-17
[patent_title] => 'Method for retransmitting fragmented packets'
[patent_app_type] => utility
[patent_app_number] => 13/720761
[patent_app_country] => US
[patent_app_date] => 2012-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 4927
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13720761
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/720761 | Method for retransmitting fragmented packets | Dec 18, 2012 | Issued |
Array
(
[id] => 9879032
[patent_doc_number] => 08966328
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-02-24
[patent_title] => 'Detecting a memory device defect'
[patent_app_type] => utility
[patent_app_number] => 13/716992
[patent_app_country] => US
[patent_app_date] => 2012-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2777
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716992
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/716992 | Detecting a memory device defect | Dec 16, 2012 | Issued |
Array
(
[id] => 9947631
[patent_doc_number] => 08996959
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-31
[patent_title] => 'Adaptive copy-back method and storage device using same'
[patent_app_type] => utility
[patent_app_number] => 13/716360
[patent_app_country] => US
[patent_app_date] => 2012-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 7964
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716360
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/716360 | Adaptive copy-back method and storage device using same | Dec 16, 2012 | Issued |
Array
(
[id] => 8893793
[patent_doc_number] => 20130166977
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-27
[patent_title] => 'SECURE LOW PIN COUNT SCAN'
[patent_app_type] => utility
[patent_app_number] => 13/715854
[patent_app_country] => US
[patent_app_date] => 2012-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3830
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13715854
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/715854 | Secure low pin count scan | Dec 13, 2012 | Issued |
Array
(
[id] => 9980562
[patent_doc_number] => 09026893
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-05-05
[patent_title] => 'Dynamically assigning inactive pages not used in Reed-Solomon code in non-volatile solid-state storage array'
[patent_app_type] => utility
[patent_app_number] => 13/713561
[patent_app_country] => US
[patent_app_date] => 2012-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4092
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13713561
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/713561 | Dynamically assigning inactive pages not used in Reed-Solomon code in non-volatile solid-state storage array | Dec 12, 2012 | Issued |
Array
(
[id] => 9891640
[patent_doc_number] => 08977915
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-10
[patent_title] => 'pBIST engine with reduced SRAM testing bus width'
[patent_app_type] => utility
[patent_app_number] => 13/709247
[patent_app_country] => US
[patent_app_date] => 2012-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2551
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13709247
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/709247 | pBIST engine with reduced SRAM testing bus width | Dec 9, 2012 | Issued |
Array
(
[id] => 10575905
[patent_doc_number] => 09298548
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-03-29
[patent_title] => 'Distributed computing in a distributed storage and task network'
[patent_app_type] => utility
[patent_app_number] => 13/707428
[patent_app_country] => US
[patent_app_date] => 2012-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 78
[patent_figures_cnt] => 83
[patent_no_of_words] => 61821
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13707428
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/707428 | Distributed computing in a distributed storage and task network | Dec 5, 2012 | Issued |
Array
(
[id] => 9513320
[patent_doc_number] => 20140149812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-29
[patent_title] => 'SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A DEBUG MODE OF OPERATION'
[patent_app_type] => utility
[patent_app_number] => 13/685875
[patent_app_country] => US
[patent_app_date] => 2012-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6403
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685875
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/685875 | SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A DEBUG MODE OF OPERATION | Nov 26, 2012 | Abandoned |
Array
(
[id] => 10301208
[patent_doc_number] => 20150186208
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'MEMORY CONTROL APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/423841
[patent_app_country] => US
[patent_app_date] => 2012-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 15685
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14423841
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/423841 | Memory control apparatus | Nov 4, 2012 | Issued |