Search

Elly Gerald Stoica

Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )

Most Active Art Unit
1647
Art Unit(s)
1647, 1646
Total Applications
1381
Issued Applications
805
Pending Applications
99
Abandoned Applications
477

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16934738 [patent_doc_number] => 20210200627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => INTEGRITY CHECK DEVICE FOR SAFETY SENSITIVE DATA AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/943185 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943185 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943185
Integrity check device for safety sensitive data and electronic device including the same Jul 29, 2020 Issued
Array ( [id] => 17358704 [patent_doc_number] => 20220019500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => FUSE LOGIC TO PERFORM SELECTIVELY ENABLED ECC DECODING [patent_app_type] => utility [patent_app_number] => 16/929253 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929253 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929253
Fuse logic to perform selectively enabled ECC decoding Jul 14, 2020 Issued
Array ( [id] => 17144987 [patent_doc_number] => 20210313000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => APPARATUS AND METHOD FOR TESTING A DEFECT OF A MEMORY MODULE AND A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/919113 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16919113 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/919113
Apparatus and method for testing a defect of a memory module and a memory system Jul 1, 2020 Issued
Array ( [id] => 18000733 [patent_doc_number] => 11501844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Memory device and test method thereof [patent_app_type] => utility [patent_app_number] => 16/912002 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7482 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/912002
Memory device and test method thereof Jun 24, 2020 Issued
Array ( [id] => 17277687 [patent_doc_number] => 20210383885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => MEMORY DEVICE AND METHOD FOR USING SHARED LATCH ELEMENTS THEREOF [patent_app_type] => utility [patent_app_number] => 16/891326 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8668 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891326 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891326
Memory device and method for using shared latch elements thereof Jun 2, 2020 Issued
Array ( [id] => 17848622 [patent_doc_number] => 11438011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Signature-enabled polar encoder and decoder [patent_app_type] => utility [patent_app_number] => 16/882623 [patent_app_country] => US [patent_app_date] => 2020-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7832 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882623 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882623
Signature-enabled polar encoder and decoder May 24, 2020 Issued
Array ( [id] => 16224757 [patent_doc_number] => 20200249874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => High Speed Data Packet Flow Processing [patent_app_type] => utility [patent_app_number] => 16/854071 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854071 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854071
High speed data packet flow processing Apr 20, 2020 Issued
Array ( [id] => 17653451 [patent_doc_number] => 11356201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => SPC sensor interface with partial parity protection [patent_app_type] => utility [patent_app_number] => 16/819450 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 9572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819450 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/819450
SPC sensor interface with partial parity protection Mar 15, 2020 Issued
Array ( [id] => 17085260 [patent_doc_number] => 20210280267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => Configurable Soft Post-Package Repair (SPPR) Schemes [patent_app_type] => utility [patent_app_number] => 16/811691 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/811691
Configurable soft post-package repair (SPPR) schemes Mar 5, 2020 Issued
Array ( [id] => 17572217 [patent_doc_number] => 11320482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Secure scan entry [patent_app_type] => utility [patent_app_number] => 16/801447 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4186 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801447 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/801447
Secure scan entry Feb 25, 2020 Issued
Array ( [id] => 16022655 [patent_doc_number] => 20200186171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => DATA WRITING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/788320 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788320
Data writing method, memory controlling circuit unit and memory storage device Feb 11, 2020 Issued
Array ( [id] => 15972337 [patent_doc_number] => 20200169920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => INFORMATION PROCESSING DEVICE, COMMUNICATION SYSTEM, AND INFORMATION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 16/775284 [patent_app_country] => US [patent_app_date] => 2020-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16775284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/775284
Information processing device, communication system, and information processing method Jan 28, 2020 Issued
Array ( [id] => 15901261 [patent_doc_number] => 20200150149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => TESTING INTERPOSER METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 16/747055 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747055 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747055
Interposer, Test Access Port, First and Second Through Silicon Vias Jan 19, 2020 Issued
Array ( [id] => 15905481 [patent_doc_number] => 20200152261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => METHODS AND APPARATUS FOR REDUCED AREA CONTROL REGISTER CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/744412 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744412
Methods and apparatus for reduced area control register circuit Jan 15, 2020 Issued
Array ( [id] => 16904545 [patent_doc_number] => 20210183461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => DATA COMPRESSION FOR GLOBAL COLUMN REPAIR [patent_app_type] => utility [patent_app_number] => 16/716366 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16716366 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/716366
Data compression for global column repair Dec 15, 2019 Issued
Array ( [id] => 16787893 [patent_doc_number] => 10990326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => High-speed replay of captured data packets [patent_app_type] => utility [patent_app_number] => 16/705884 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 17956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705884 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705884
High-speed replay of captured data packets Dec 5, 2019 Issued
Array ( [id] => 16095499 [patent_doc_number] => 20200201736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => INFORMATION PROCESSING APPARATUS AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/691684 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691684 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/691684
Information processing apparatus and control method Nov 21, 2019 Issued
Array ( [id] => 16894887 [patent_doc_number] => 11036438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Efficient storage architecture for high speed packet capture [patent_app_type] => utility [patent_app_number] => 16/689867 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 18544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689867 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689867
Efficient storage architecture for high speed packet capture Nov 19, 2019 Issued
Array ( [id] => 17304007 [patent_doc_number] => 20210399846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => APPARATUS, METHOD AND COMPUTER PROGRAM FOR PACKET DUPLICATION [patent_app_type] => utility [patent_app_number] => 17/287664 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17287664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/287664
APPARATUS, METHOD AND COMPUTER PROGRAM FOR PACKET DUPLICATION Oct 31, 2019 Abandoned
Array ( [id] => 17032575 [patent_doc_number] => 11094392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Testing of fault detection circuit [patent_app_type] => utility [patent_app_number] => 16/601303 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601303 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601303
Testing of fault detection circuit Oct 13, 2019 Issued
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