Elly Gerald Stoica

Array ( [id] => 6105270 [patent_doc_number] => 20110167323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'Error-Correcting Apparatus and Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/683915 [patent_app_country] => US [patent_app_date] => 2010-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5989 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20110167323.pdf [firstpage_image] =>[orig_patent_app_number] => 12683915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6105237 [patent_doc_number] => 20110167308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS' [patent_app_type] => utility [patent_app_number] => 12/683365 [patent_app_country] => US [patent_app_date] => 2010-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10114 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20110167308.pdf [firstpage_image] =>[orig_patent_app_number] => 12683365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8594953 [patent_doc_number] => 08352836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Error addition apparatus' [patent_app_type] => utility [patent_app_number] => 12/683072 [patent_app_country] => US [patent_app_date] => 2010-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2874 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12683072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6647209 [patent_doc_number] => 20100174958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'Test circuit including tap controller selectively outputting test signal based on mode and shift signals' [patent_app_type] => utility [patent_app_number] => 12/654801 [patent_app_country] => US [patent_app_date] => 2010-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6738 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174958.pdf [firstpage_image] =>[orig_patent_app_number] => 12654801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6447273 [patent_doc_number] => 20100169725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'MEMORY MODULE TESTER' [patent_app_type] => utility [patent_app_number] => 12/648588 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3226 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20100169725.pdf [firstpage_image] =>[orig_patent_app_number] => 12648588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8273174 [patent_doc_number] => 08214698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Solid state storage system with improved data merging efficiency and control method thereof' [patent_app_type] => utility [patent_app_number] => 12/648346 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3294 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12648346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6166746 [patent_doc_number] => 20110161759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'SCAN ARCHITECTURE AND DESIGN METHODOLOGY YIELDING SIGNIFICANT REDUCTION IN SCAN AREA AND POWER OVERHEAD' [patent_app_type] => utility [patent_app_number] => 12/648812 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161759.pdf [firstpage_image] =>[orig_patent_app_number] => 12648812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6447292 [patent_doc_number] => 20100169727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'EDA TOOL, SEMICONDUCTOR DEVICE, AND SCAN CHAIN CONFIGURATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/647475 [patent_app_country] => US [patent_app_date] => 2009-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5964 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20100169727.pdf [firstpage_image] =>[orig_patent_app_number] => 12647475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8693239 [patent_doc_number] => 08392775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Shift register circuit' [patent_app_type] => utility [patent_app_number] => 12/640012 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10409 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12640012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6449587 [patent_doc_number] => 20100153772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'COUNT DATA RECORDING DEVICE, AND METHOD AND PROGRAM FOR RECORDING COUNT DATA' [patent_app_type] => utility [patent_app_number] => 12/638678 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 19746 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20100153772.pdf [firstpage_image] =>[orig_patent_app_number] => 12638678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9947617 [patent_doc_number] => 08996946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Application of fountain forward error correction codes in multi-link multi-path mobile networks' [patent_app_type] => utility [patent_app_number] => 13/514400 [patent_app_country] => US [patent_app_date] => 2009-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4783 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13514400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6447288 [patent_doc_number] => 20100169726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'INFORMATION PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/613932 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20100169726.pdf [firstpage_image] =>[orig_patent_app_number] => 12613932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8561878 [patent_doc_number] => 08335949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Tunable early-stopping for decoders' [patent_app_type] => utility [patent_app_number] => 12/614292 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 8564 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12614292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5948893 [patent_doc_number] => 20110107160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'TIME-BASED TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 12/608476 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20110107160.pdf [firstpage_image] =>[orig_patent_app_number] => 12608476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5990792 [patent_doc_number] => 20110099442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIONED SCAN CHAINS' [patent_app_type] => utility [patent_app_number] => 12/604397 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20110099442.pdf [firstpage_image] =>[orig_patent_app_number] => 12604397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9012501 [patent_doc_number] => 08527822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'System and method for single terminal boundary scan' [patent_app_type] => utility [patent_app_number] => 12/581651 [patent_app_country] => US [patent_app_date] => 2009-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6815 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12581651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8235575 [patent_doc_number] => 08201038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Integrating design for reliability technology into integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/568968 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4896 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201038.pdf [firstpage_image] =>[orig_patent_app_number] => 12568968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8985192 [patent_doc_number] => 08516322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-20 [patent_title] => 'Automatic test pattern generation system for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/568136 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5981 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12568136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6204122 [patent_doc_number] => 20110066908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'SIMILARITY DETECTION FOR ERROR REPORTS' [patent_app_type] => utility [patent_app_number] => 12/561608 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066908.pdf [firstpage_image] =>[orig_patent_app_number] => 12561608 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8693251 [patent_doc_number] => 08392787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding' [patent_app_type] => utility [patent_app_number] => 12/561374 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 10758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12561374 [rel_patent_id] =>[rel_patent_doc_number] =>)