Search

Elly Gerald Stoica

Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )

Most Active Art Unit
1647
Art Unit(s)
1647, 1646
Total Applications
1381
Issued Applications
805
Pending Applications
99
Abandoned Applications
477

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6361697 [patent_doc_number] => 20100079184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Sequential circuit with error detection' [patent_app_type] => utility [patent_app_number] => 12/286067 [patent_app_country] => US [patent_app_date] => 2008-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2631 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20100079184.pdf [firstpage_image] =>[orig_patent_app_number] => 12286067 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/286067
Sequential circuit with error detection Sep 25, 2008 Issued
Array ( [id] => 8775538 [patent_doc_number] => 08429514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-23 [patent_title] => 'Dynamic load balancing of distributed parity in a RAID array' [patent_app_type] => utility [patent_app_number] => 12/237138 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7070 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12237138 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/237138
Dynamic load balancing of distributed parity in a RAID array Sep 23, 2008 Issued
Array ( [id] => 4854606 [patent_doc_number] => 20080320349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'eFuse Programming Data Alignment Verification Apparatus and Method' [patent_app_type] => utility [patent_app_number] => 12/202584 [patent_app_country] => US [patent_app_date] => 2008-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320349.pdf [firstpage_image] =>[orig_patent_app_number] => 12202584 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/202584
eFuse programming data alignment verification Sep 1, 2008 Issued
Array ( [id] => 4951152 [patent_doc_number] => 20080307278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'APPARATUS FOR EFFICIENTLY LOADING SCAN AND NON-SCAN MEMORY ELEMENTS' [patent_app_type] => utility [patent_app_number] => 12/187481 [patent_app_country] => US [patent_app_date] => 2008-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1877 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307278.pdf [firstpage_image] =>[orig_patent_app_number] => 12187481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/187481
Apparatus for efficiently loading scan and non-scan memory elements Aug 6, 2008 Issued
Array ( [id] => 4841641 [patent_doc_number] => 20080282127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'HYBRID AUTOMATIC REPEAT REQUEST SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/177933 [patent_app_country] => US [patent_app_date] => 2008-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 19361 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282127.pdf [firstpage_image] =>[orig_patent_app_number] => 12177933 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177933
Hybrid automatic repeat request system and method Jul 22, 2008 Issued
Array ( [id] => 8109475 [patent_doc_number] => 08156391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Data controlling in the MBIST chain architecture' [patent_app_type] => utility [patent_app_number] => 12/167305 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9362 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156391.pdf [firstpage_image] =>[orig_patent_app_number] => 12167305 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/167305
Data controlling in the MBIST chain architecture Jul 2, 2008 Issued
Array ( [id] => 8220241 [patent_doc_number] => 08195995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Integrated circuit and method of protecting a circuit part of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/166906 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4985 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/195/08195995.pdf [firstpage_image] =>[orig_patent_app_number] => 12166906 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166906
Integrated circuit and method of protecting a circuit part of an integrated circuit Jul 1, 2008 Issued
Array ( [id] => 8001253 [patent_doc_number] => 08082474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Bit shadowing in a memory system' [patent_app_type] => utility [patent_app_number] => 12/165799 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16286 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082474.pdf [firstpage_image] =>[orig_patent_app_number] => 12165799 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165799
Bit shadowing in a memory system Jun 30, 2008 Issued
Array ( [id] => 5312052 [patent_doc_number] => 20090019333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Generation of parity-check matrices' [patent_app_type] => utility [patent_app_number] => 12/216229 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10626 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019333.pdf [firstpage_image] =>[orig_patent_app_number] => 12216229 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/216229
Generation of parity-check matrices Jun 30, 2008 Abandoned
Array ( [id] => 6640432 [patent_doc_number] => 20100005349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'ENHANCED MICROPROCESSOR INTERCONNECT WITH BIT SHADOWING' [patent_app_type] => utility [patent_app_number] => 12/165848 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11143 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20100005349.pdf [firstpage_image] =>[orig_patent_app_number] => 12165848 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165848
Enhanced microprocessor interconnect with bit shadowing Jun 30, 2008 Issued
Array ( [id] => 8019843 [patent_doc_number] => 08139430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Power-on initialization and test for a cascade interconnect memory system' [patent_app_type] => utility [patent_app_number] => 12/166139 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 20913 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/139/08139430.pdf [firstpage_image] =>[orig_patent_app_number] => 12166139 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166139
Power-on initialization and test for a cascade interconnect memory system Jun 30, 2008 Issued
Array ( [id] => 5433975 [patent_doc_number] => 20090168561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'TEST ENTRY CIRCUIT AND METHOD FOR GENERATING TEST ENTRY SIGNAL' [patent_app_type] => utility [patent_app_number] => 12/165008 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4290 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168561.pdf [firstpage_image] =>[orig_patent_app_number] => 12165008 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165008
Test entry circuit and method for generating test entry signal Jun 29, 2008 Issued
Array ( [id] => 5467637 [patent_doc_number] => 20090327837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'NAND error management' [patent_app_type] => utility [patent_app_number] => 12/215915 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4575 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327837.pdf [firstpage_image] =>[orig_patent_app_number] => 12215915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/215915
NAND error management Jun 29, 2008 Abandoned
Array ( [id] => 8580966 [patent_doc_number] => 08347198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Semiconductor memory device having capability of stable initial operation' [patent_app_type] => utility [patent_app_number] => 12/217064 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12217064 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/217064
Semiconductor memory device having capability of stable initial operation Jun 29, 2008 Issued
Array ( [id] => 8546476 [patent_doc_number] => 08321779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Semiconductor device and method for operating the same' [patent_app_type] => utility [patent_app_number] => 12/215726 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7774 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12215726 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/215726
Semiconductor device and method for operating the same Jun 29, 2008 Issued
Array ( [id] => 5399778 [patent_doc_number] => 20090319841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE' [patent_app_type] => utility [patent_app_number] => 12/144703 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4449 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0319/20090319841.pdf [firstpage_image] =>[orig_patent_app_number] => 12144703 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144703
Design structure and apparatus for a robust embedded interface Jun 23, 2008 Issued
Array ( [id] => 6447913 [patent_doc_number] => 20100189187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'METHOD FOR DATA RATE MATCHING' [patent_app_type] => utility [patent_app_number] => 12/665582 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6617 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20100189187.pdf [firstpage_image] =>[orig_patent_app_number] => 12665582 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/665582
Method for data rate matching Jun 19, 2008 Issued
Array ( [id] => 8366698 [patent_doc_number] => 08255772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'Adaptive memory scrub rate' [patent_app_type] => utility [patent_app_number] => 12/214283 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12214283 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/214283
Adaptive memory scrub rate Jun 17, 2008 Issued
Array ( [id] => 5437895 [patent_doc_number] => 20090172482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'METHODS FOR PERFORMING FAIL TEST, BLOCK MANAGEMENT, ERASING AND PROGRAMMING IN A NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/130994 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172482.pdf [firstpage_image] =>[orig_patent_app_number] => 12130994 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130994
Methods for performing fail test, block management, erasing and programming in a nonvolatile memory device May 29, 2008 Issued
Array ( [id] => 8022807 [patent_doc_number] => 08140922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Method for correlating an error message from a PCI express endpoint' [patent_app_type] => utility [patent_app_number] => 12/123780 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3208 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/140/08140922.pdf [firstpage_image] =>[orig_patent_app_number] => 12123780 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/123780
Method for correlating an error message from a PCI express endpoint May 19, 2008 Issued
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