Search

Elly Gerald Stoica

Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )

Most Active Art Unit
1647
Art Unit(s)
1647, 1646
Total Applications
1381
Issued Applications
805
Pending Applications
99
Abandoned Applications
477

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8594960 [patent_doc_number] => 08352843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Method and apparatus for coding a communication signal' [patent_app_type] => utility [patent_app_number] => 11/962762 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 6337 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11962762 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962762
Method and apparatus for coding a communication signal Dec 20, 2007 Issued
Array ( [id] => 4500058 [patent_doc_number] => 07904762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Error detection on medical high speed transmission routes' [patent_app_type] => utility [patent_app_number] => 11/962604 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4255 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904762.pdf [firstpage_image] =>[orig_patent_app_number] => 11962604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962604
Error detection on medical high speed transmission routes Dec 20, 2007 Issued
Array ( [id] => 4869052 [patent_doc_number] => 20080148111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Method and apparatus for recovering protocol error in a wireless communications system' [patent_app_type] => utility [patent_app_number] => 12/003046 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2113 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148111.pdf [firstpage_image] =>[orig_patent_app_number] => 12003046 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/003046
Method and apparatus for recovering protocol error in a wireless communications system Dec 18, 2007 Abandoned
Array ( [id] => 4550392 [patent_doc_number] => 07873883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-18 [patent_title] => 'Method for scrubbing storage in a computer memory' [patent_app_type] => utility [patent_app_number] => 11/959727 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/873/07873883.pdf [firstpage_image] =>[orig_patent_app_number] => 11959727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959727
Method for scrubbing storage in a computer memory Dec 18, 2007 Issued
Array ( [id] => 7532633 [patent_doc_number] => 07844867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-30 [patent_title] => 'Combined processor access and built in self test in hierarchical memory systems' [patent_app_type] => utility [patent_app_number] => 11/959705 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844867.pdf [firstpage_image] =>[orig_patent_app_number] => 11959705 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959705
Combined processor access and built in self test in hierarchical memory systems Dec 18, 2007 Issued
Array ( [id] => 4559689 [patent_doc_number] => 07877657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-25 [patent_title] => 'Look-ahead built-in self tests' [patent_app_type] => utility [patent_app_number] => 11/960618 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877657.pdf [firstpage_image] =>[orig_patent_app_number] => 11960618 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960618
Look-ahead built-in self tests Dec 18, 2007 Issued
Array ( [id] => 4881980 [patent_doc_number] => 20080155363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'BIST CIRCUIT DEVICE AND SELF TEST METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/958737 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155363.pdf [firstpage_image] =>[orig_patent_app_number] => 11958737 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958737
BIST CIRCUIT DEVICE AND SELF TEST METHOD THEREOF Dec 17, 2007 Abandoned
Array ( [id] => 4487084 [patent_doc_number] => 07870448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'In system diagnostics through scan matrix' [patent_app_type] => utility [patent_app_number] => 11/958468 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870448.pdf [firstpage_image] =>[orig_patent_app_number] => 11958468 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958468
In system diagnostics through scan matrix Dec 17, 2007 Issued
Array ( [id] => 4443532 [patent_doc_number] => 07900102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'High-speed programming of memory devices' [patent_app_type] => utility [patent_app_number] => 11/957970 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8939 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900102.pdf [firstpage_image] =>[orig_patent_app_number] => 11957970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/957970
High-speed programming of memory devices Dec 16, 2007 Issued
Array ( [id] => 4508657 [patent_doc_number] => 07958415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Semiconductor integrated circuit and method of detecting fail path thereof' [patent_app_type] => utility [patent_app_number] => 11/958333 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4354 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958415.pdf [firstpage_image] =>[orig_patent_app_number] => 11958333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958333
Semiconductor integrated circuit and method of detecting fail path thereof Dec 16, 2007 Issued
Array ( [id] => 7547985 [patent_doc_number] => 08055966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-08 [patent_title] => 'Built-in-self-repair arrangement for a single multiple-integrated circuit package and methods thereof' [patent_app_type] => utility [patent_app_number] => 11/958284 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/055/08055966.pdf [firstpage_image] =>[orig_patent_app_number] => 11958284 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958284
Built-in-self-repair arrangement for a single multiple-integrated circuit package and methods thereof Dec 16, 2007 Issued
Array ( [id] => 4557604 [patent_doc_number] => 07890817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Protective system for an installation and a method for checking a protective system' [patent_app_type] => utility [patent_app_number] => 12/001948 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 7537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/890/07890817.pdf [firstpage_image] =>[orig_patent_app_number] => 12001948 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/001948
Protective system for an installation and a method for checking a protective system Dec 12, 2007 Issued
Array ( [id] => 9062922 [patent_doc_number] => 08549376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-01 [patent_title] => 'Vector turbo codes' [patent_app_type] => utility [patent_app_number] => 12/001818 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4920 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12001818 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/001818
Vector turbo codes Dec 12, 2007 Issued
Array ( [id] => 4865351 [patent_doc_number] => 20080144410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Redundancy circuit and semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/000373 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13867 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20080144410.pdf [firstpage_image] =>[orig_patent_app_number] => 12000373 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000373
Redundancy circuit and semiconductor memory device Dec 11, 2007 Issued
Array ( [id] => 8208236 [patent_doc_number] => 08190961 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-29 [patent_title] => 'System and method for using pilot signals in non-volatile memory devices' [patent_app_type] => utility [patent_app_number] => 11/986872 [patent_app_country] => US [patent_app_date] => 2007-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 8960 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/190/08190961.pdf [firstpage_image] =>[orig_patent_app_number] => 11986872 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/986872
System and method for using pilot signals in non-volatile memory devices Nov 26, 2007 Issued
Array ( [id] => 4966874 [patent_doc_number] => 20080109694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Method and apparatus for performing uplink transmission in a multi-input multi-output user equipment of a wireless communications system' [patent_app_type] => utility [patent_app_number] => 11/979692 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2007 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109694.pdf [firstpage_image] =>[orig_patent_app_number] => 11979692 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/979692
Method and apparatus for performing uplink transmission in a multi-input multi-output user equipment of a wireless communications system Nov 6, 2007 Abandoned
Array ( [id] => 7521083 [patent_doc_number] => 07975192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Reading memory cells using multiple thresholds' [patent_app_type] => utility [patent_app_number] => 11/995814 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 13761 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975192.pdf [firstpage_image] =>[orig_patent_app_number] => 11995814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/995814
Reading memory cells using multiple thresholds Oct 29, 2007 Issued
Array ( [id] => 9077540 [patent_doc_number] => 08555132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Modification of error statistics behind equalizer to improve inter-working with different FEC codes' [patent_app_type] => utility [patent_app_number] => 11/924397 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 9389 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11924397 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/924397
Modification of error statistics behind equalizer to improve inter-working with different FEC codes Oct 24, 2007 Issued
Array ( [id] => 8959096 [patent_doc_number] => 08504890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Scheduling for LDPC decoding' [patent_app_type] => utility [patent_app_number] => 11/876868 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9431 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11876868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/876868
Scheduling for LDPC decoding Oct 22, 2007 Issued
Array ( [id] => 8149351 [patent_doc_number] => 08166366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-24 [patent_title] => 'Partial configuration of programmable circuitry with validation' [patent_app_type] => utility [patent_app_number] => 11/975961 [patent_app_country] => US [patent_app_date] => 2007-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166366.pdf [firstpage_image] =>[orig_patent_app_number] => 11975961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/975961
Partial configuration of programmable circuitry with validation Oct 21, 2007 Issued
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