Search

Elly Gerald Stoica

Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )

Most Active Art Unit
1647
Art Unit(s)
1647, 1646
Total Applications
1381
Issued Applications
805
Pending Applications
99
Abandoned Applications
477

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4854605 [patent_doc_number] => 20080320348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Launch-On-Shift Support for On-Chip-Clocking' [patent_app_type] => utility [patent_app_number] => 11/767606 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6236 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320348.pdf [firstpage_image] =>[orig_patent_app_number] => 11767606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/767606
Launch-on-shift support for on-chip-clocking Jun 24, 2007 Issued
Array ( [id] => 106993 [patent_doc_number] => 07730375 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Method and apparatus for controlling operating modes of an electronic device' [patent_app_type] => utility [patent_app_number] => 11/768092 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8617 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730375.pdf [firstpage_image] =>[orig_patent_app_number] => 11768092 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768092
Method and apparatus for controlling operating modes of an electronic device Jun 24, 2007 Issued
Array ( [id] => 8536165 [patent_doc_number] => 08312330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'System and method for testing wireless devices' [patent_app_type] => utility [patent_app_number] => 11/766282 [patent_app_country] => US [patent_app_date] => 2007-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6145 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11766282 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/766282
System and method for testing wireless devices Jun 20, 2007 Issued
Array ( [id] => 5212164 [patent_doc_number] => 20070250748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Logic circuit protected against transitory perturbations' [patent_app_type] => utility [patent_app_number] => 11/820714 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6993 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20070250748.pdf [firstpage_image] =>[orig_patent_app_number] => 11820714 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/820714
Logic circuit protected against transitory perturbations Jun 18, 2007 Issued
Array ( [id] => 4774004 [patent_doc_number] => 20080059666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'MICROCONTROLLER AND DEBUGGING METHOD' [patent_app_type] => utility [patent_app_number] => 11/764949 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3086 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059666.pdf [firstpage_image] =>[orig_patent_app_number] => 11764949 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764949
MICROCONTROLLER AND DEBUGGING METHOD Jun 18, 2007 Abandoned
Array ( [id] => 146885 [patent_doc_number] => 07694194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/764862 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5902 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694194.pdf [firstpage_image] =>[orig_patent_app_number] => 11764862 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764862
Semiconductor device Jun 18, 2007 Issued
Array ( [id] => 157925 [patent_doc_number] => 07685480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Content addressable memory having redundant row isolated noise circuit and method of use' [patent_app_type] => utility [patent_app_number] => 11/764668 [patent_app_country] => US [patent_app_date] => 2007-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685480.pdf [firstpage_image] =>[orig_patent_app_number] => 11764668 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764668
Content addressable memory having redundant row isolated noise circuit and method of use Jun 17, 2007 Issued
Array ( [id] => 4774191 [patent_doc_number] => 20080059853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Semiconductor Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/749968 [patent_app_country] => US [patent_app_date] => 2007-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4660 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059853.pdf [firstpage_image] =>[orig_patent_app_number] => 11749968 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/749968
Semiconductor Integrated Circuit May 16, 2007 Abandoned
Array ( [id] => 86758 [patent_doc_number] => 07747916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'JTAG interface' [patent_app_type] => utility [patent_app_number] => 11/748415 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3253 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/747/07747916.pdf [firstpage_image] =>[orig_patent_app_number] => 11748415 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/748415
JTAG interface May 13, 2007 Issued
Array ( [id] => 4862442 [patent_doc_number] => 20080270857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'BOUNDARY SCAN CONNECTOR TEST METHOD CAPABLE OF FULLY UTILIZING TEST I/O MODULES' [patent_app_type] => utility [patent_app_number] => 11/747922 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3205 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270857.pdf [firstpage_image] =>[orig_patent_app_number] => 11747922 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/747922
Boundary scan connector test method capable of fully utilizing test I/O modules May 13, 2007 Issued
Array ( [id] => 7799103 [patent_doc_number] => RE043231 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2012-03-06 [patent_title] => 'System and method for joint source-channel encoding, with symbol, decoding and error correction' [patent_app_type] => reissue [patent_app_number] => 11/798175 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 11419 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/043/RE043231.pdf [firstpage_image] =>[orig_patent_app_number] => 11798175 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/798175
System and method for joint source-channel encoding, with symbol, decoding and error correction May 9, 2007 Issued
Array ( [id] => 4488670 [patent_doc_number] => 07908528 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-15 [patent_title] => 'Phase-detector-less method and apparatus for minimizing skew between bonded channel groups' [patent_app_type] => utility [patent_app_number] => 11/747152 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4859 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/908/07908528.pdf [firstpage_image] =>[orig_patent_app_number] => 11747152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/747152
Phase-detector-less method and apparatus for minimizing skew between bonded channel groups May 9, 2007 Issued
Array ( [id] => 4841637 [patent_doc_number] => 20080282123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'System and Method of Multi-Frequency Integrated Circuit Testing' [patent_app_type] => utility [patent_app_number] => 11/746715 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282123.pdf [firstpage_image] =>[orig_patent_app_number] => 11746715 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/746715
System and Method of Multi-Frequency Integrated Circuit Testing May 9, 2007 Abandoned
Array ( [id] => 4841624 [patent_doc_number] => 20080282110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'SCAN CLOCK ARCHITECTURE SUPPORTING SLOW SPEED SCAN, AT SPEED SCAN, AND LOGIC BIST' [patent_app_type] => utility [patent_app_number] => 11/746477 [patent_app_country] => US [patent_app_date] => 2007-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3249 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282110.pdf [firstpage_image] =>[orig_patent_app_number] => 11746477 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/746477
SCAN CLOCK ARCHITECTURE SUPPORTING SLOW SPEED SCAN, AT SPEED SCAN, AND LOGIC BIST May 8, 2007 Abandoned
Array ( [id] => 4841636 [patent_doc_number] => 20080282122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'SINGLE SCAN CLOCK IN A MULTI-CLOCK DOMAIN' [patent_app_type] => utility [patent_app_number] => 11/746450 [patent_app_country] => US [patent_app_date] => 2007-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2927 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282122.pdf [firstpage_image] =>[orig_patent_app_number] => 11746450 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/746450
SINGLE SCAN CLOCK IN A MULTI-CLOCK DOMAIN May 8, 2007 Abandoned
Array ( [id] => 4841621 [patent_doc_number] => 20080282107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'Method and Apparatus for Repairing Memory' [patent_app_type] => utility [patent_app_number] => 11/745244 [patent_app_country] => US [patent_app_date] => 2007-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1856 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282107.pdf [firstpage_image] =>[orig_patent_app_number] => 11745244 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/745244
Method and apparatus for repairing memory May 6, 2007 Issued
Array ( [id] => 366723 [patent_doc_number] => 07484143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'System and method for providing testing and failure analysis of integrated circuit memory devices' [patent_app_type] => utility [patent_app_number] => 11/800656 [patent_app_country] => US [patent_app_date] => 2007-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 6243 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/484/07484143.pdf [firstpage_image] =>[orig_patent_app_number] => 11800656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/800656
System and method for providing testing and failure analysis of integrated circuit memory devices May 6, 2007 Issued
Array ( [id] => 175667 [patent_doc_number] => 07661050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Method and system for formal verification of partial good self test fencing structures' [patent_app_type] => utility [patent_app_number] => 11/744392 [patent_app_country] => US [patent_app_date] => 2007-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 10998 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/661/07661050.pdf [firstpage_image] =>[orig_patent_app_number] => 11744392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/744392
Method and system for formal verification of partial good self test fencing structures May 3, 2007 Issued
Array ( [id] => 7510581 [patent_doc_number] => 08037370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Data transmission apparatus with information skew and redundant control information and method' [patent_app_type] => utility [patent_app_number] => 11/743479 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5566 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037370.pdf [firstpage_image] =>[orig_patent_app_number] => 11743479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/743479
Data transmission apparatus with information skew and redundant control information and method May 1, 2007 Issued
Array ( [id] => 5114969 [patent_doc_number] => 20070198885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Semiconductor integrated circuit and test system for testing the same' [patent_app_type] => utility [patent_app_number] => 11/785624 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3611 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20070198885.pdf [firstpage_image] =>[orig_patent_app_number] => 11785624 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/785624
Semiconductor integrated circuit and test system for testing the same Apr 18, 2007 Abandoned
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