Elly Gerald Stoica

Array ( [id] => 801653 [patent_doc_number] => 07426663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Semiconductor integrated circuit and testing method thereof' [patent_app_type] => utility [patent_app_number] => 11/785213 [patent_app_country] => US [patent_app_date] => 2007-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7448 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/426/07426663.pdf [firstpage_image] =>[orig_patent_app_number] => 11785213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4942359 [patent_doc_number] => 20080079682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'CONTROL CIRCUIT FOR RELEASING RESIDUAL CHARGES' [patent_app_type] => utility [patent_app_number] => 11/689735 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2165 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20080079682.pdf [firstpage_image] =>[orig_patent_app_number] => 11689735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 171932 [patent_doc_number] => 07669100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'System and method for testing and providing an integrated circuit having multiple modules or submodules' [patent_app_type] => utility [patent_app_number] => 11/683607 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669100.pdf [firstpage_image] =>[orig_patent_app_number] => 11683607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9251900 [patent_doc_number] => 08615691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => 'Process for improving design-limited yield by localizing potential faults from production test data' [patent_app_type] => utility [patent_app_number] => 11/682314 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5820 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11682314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5190464 [patent_doc_number] => 20070168773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Semiconductor memory unit with repair circuit' [patent_app_type] => utility [patent_app_number] => 11/712443 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3877 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168773.pdf [firstpage_image] =>[orig_patent_app_number] => 11712443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5114289 [patent_doc_number] => 20070198205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'TEST APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/681071 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4017 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20070198205.pdf [firstpage_image] =>[orig_patent_app_number] => 11681071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 188524 [patent_doc_number] => 07650547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Apparatus for locating a defect in a scan chain while testing digital logic' [patent_app_type] => utility [patent_app_number] => 11/680134 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3164 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/650/07650547.pdf [firstpage_image] =>[orig_patent_app_number] => 11680134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 188530 [patent_doc_number] => 07650550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Over temperature detection apparatus and method thereof' [patent_app_type] => utility [patent_app_number] => 11/679242 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/650/07650550.pdf [firstpage_image] =>[orig_patent_app_number] => 11679242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4725618 [patent_doc_number] => 20080205159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'VERIFICATION PROCESS OF A FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 11/679205 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1813 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205159.pdf [firstpage_image] =>[orig_patent_app_number] => 11679205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7689875 [patent_doc_number] => 20070234158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'METHOD OF TESTING A SEMICONDUCTOR MEMORY DEVICE, METHOD OF DATA SERIALIZATION AND DATA SERIALIZER' [patent_app_type] => utility [patent_app_number] => 11/679809 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234158.pdf [firstpage_image] =>[orig_patent_app_number] => 11679809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5017746 [patent_doc_number] => 20070260955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'TEST AUXILIARY DEVICE IN A MEMORY MODULE' [patent_app_type] => utility [patent_app_number] => 11/677572 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7833 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20070260955.pdf [firstpage_image] =>[orig_patent_app_number] => 11677572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4811073 [patent_doc_number] => 20080191704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Method to Improve Isolation of an Open Net Fault in an Interposer Mounted Module' [patent_app_type] => utility [patent_app_number] => 11/672555 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3150 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191704.pdf [firstpage_image] =>[orig_patent_app_number] => 11672555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4847657 [patent_doc_number] => 20080184065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'METHODS AND APPARATUS FOR EMPLOYING REDUNDANT ARRAYS TO CONFIGURE NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/669918 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4352 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20080184065.pdf [firstpage_image] =>[orig_patent_app_number] => 11669918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4847649 [patent_doc_number] => 20080184057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'METHODS AND APPARATUS FOR EMPLOYING REDUNDANT ARRAYS TO CONFIGURE NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/669917 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20080184057.pdf [firstpage_image] =>[orig_patent_app_number] => 11669917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8837257 [patent_doc_number] => 08453026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures' [patent_app_type] => utility [patent_app_number] => 11/565616 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2148 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11565616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4830249 [patent_doc_number] => 20080126896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'System and Method for Device Performance Characterization in Physical and Logical Domains with AC SCAN Testing' [patent_app_type] => utility [patent_app_number] => 11/563612 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3681 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126896.pdf [firstpage_image] =>[orig_patent_app_number] => 11563612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4830250 [patent_doc_number] => 20080126897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'SYSTEM AND METHOD FOR GENERATING SELF-SYNCHRONIZED LAUNCH OF LAST SHIFT CAPTURE PULSES USING ON-CHIP PHASE LOCKED LOOP FOR AT-SPEED SCAN TESTING' [patent_app_type] => utility [patent_app_number] => 11/563484 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126897.pdf [firstpage_image] =>[orig_patent_app_number] => 11563484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 28424 [patent_doc_number] => 07797598 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Dynamic timer for testbench interface synchronization' [patent_app_type] => utility [patent_app_number] => 11/599112 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5405 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797598.pdf [firstpage_image] =>[orig_patent_app_number] => 11599112 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4905605 [patent_doc_number] => 20080115019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Circuit Timing Monitor Having A Selectable-Path Ring Oscillator' [patent_app_type] => utility [patent_app_number] => 11/559436 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20080115019.pdf [firstpage_image] =>[orig_patent_app_number] => 11559436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5024890 [patent_doc_number] => 20070150857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method and apparatus for remotely verifying memory integrity of a device' [patent_app_type] => utility [patent_app_number] => 11/593520 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3708 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150857.pdf [firstpage_image] =>[orig_patent_app_number] => 11593520 [rel_patent_id] =>[rel_patent_doc_number] =>)