Elly Gerald Stoica

Array ( [id] => 4973116 [patent_doc_number] => 20070113119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'High-Speed Transceiver Tester Incorporating Jitter Injection' [patent_app_type] => utility [patent_app_number] => 11/553035 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4343 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20070113119.pdf [firstpage_image] =>[orig_patent_app_number] => 11553035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5047509 [patent_doc_number] => 20070266183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'SAMPLING A DEVICE BUS' [patent_app_type] => utility [patent_app_number] => 11/552128 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20070266183.pdf [firstpage_image] =>[orig_patent_app_number] => 11552128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8120239 [patent_doc_number] => 08161338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Modular compaction of test responses' [patent_app_type] => utility [patent_app_number] => 11/580650 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 12930 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161338.pdf [firstpage_image] =>[orig_patent_app_number] => 11580650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 595775 [patent_doc_number] => 07458005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-25 [patent_title] => 'System and method for providing adjustable read margins in a semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/524691 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4314 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/458/07458005.pdf [firstpage_image] =>[orig_patent_app_number] => 11524691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7510592 [patent_doc_number] => 08037379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-11 [patent_title] => 'Prediction of impact on post-repair yield resulting from manufacturing process modification' [patent_app_type] => utility [patent_app_number] => 11/469353 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6886 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037379.pdf [firstpage_image] =>[orig_patent_app_number] => 11469353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 235088 [patent_doc_number] => 07600162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/508222 [patent_app_country] => US [patent_app_date] => 2006-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/600/07600162.pdf [firstpage_image] =>[orig_patent_app_number] => 11508222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 223540 [patent_doc_number] => 07610530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Test data generator, test system and method thereof' [patent_app_type] => utility [patent_app_number] => 11/508177 [patent_app_country] => US [patent_app_date] => 2006-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5712 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/610/07610530.pdf [firstpage_image] =>[orig_patent_app_number] => 11508177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 118340 [patent_doc_number] => 07716544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Path data transmission unit' [patent_app_type] => utility [patent_app_number] => 11/507892 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4561 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/716/07716544.pdf [firstpage_image] =>[orig_patent_app_number] => 11507892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4530824 [patent_doc_number] => 07913141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Power gating in integrated circuits for leakage reduction' [patent_app_type] => utility [patent_app_number] => 11/505113 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1879 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/913/07913141.pdf [firstpage_image] =>[orig_patent_app_number] => 11505113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 223529 [patent_doc_number] => 07610524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Memory with test mode output' [patent_app_type] => utility [patent_app_number] => 11/491640 [patent_app_country] => US [patent_app_date] => 2006-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9545 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/610/07610524.pdf [firstpage_image] =>[orig_patent_app_number] => 11491640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5190470 [patent_doc_number] => 20070168779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Testing of a CAM' [patent_app_type] => utility [patent_app_number] => 11/474496 [patent_app_country] => US [patent_app_date] => 2006-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8348 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168779.pdf [firstpage_image] =>[orig_patent_app_number] => 11474496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7598060 [patent_doc_number] => 07584393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Scan test circuit and method of arranging the same' [patent_app_type] => utility [patent_app_number] => 11/421885 [patent_app_country] => US [patent_app_date] => 2006-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4656 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/584/07584393.pdf [firstpage_image] =>[orig_patent_app_number] => 11421885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5012625 [patent_doc_number] => 20070283104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Concurrent Hardware Selftest for Central Storage' [patent_app_type] => utility [patent_app_number] => 11/421167 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2710 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20070283104.pdf [firstpage_image] =>[orig_patent_app_number] => 11421167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 245157 [patent_doc_number] => 07590901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Apparatus, system, and method for dynamic recovery and restoration from design defects in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/419271 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590901.pdf [firstpage_image] =>[orig_patent_app_number] => 11419271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5607108 [patent_doc_number] => 20060268624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE AND READ METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/419155 [patent_app_country] => US [patent_app_date] => 2006-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7347 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20060268624.pdf [firstpage_image] =>[orig_patent_app_number] => 11419155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4984432 [patent_doc_number] => 20070088991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Method and apparatus for verifying multi-channel data' [patent_app_type] => utility [patent_app_number] => 11/417980 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4912 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20070088991.pdf [firstpage_image] =>[orig_patent_app_number] => 11417980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7521082 [patent_doc_number] => 07975191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Nonvolatile memory device comprising a programming and deletion checking option' [patent_app_type] => utility [patent_app_number] => 11/417520 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4625 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975191.pdf [firstpage_image] =>[orig_patent_app_number] => 11417520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17540 [patent_doc_number] => 07805646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'LSI internal signal observing circuit' [patent_app_type] => utility [patent_app_number] => 11/415584 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/805/07805646.pdf [firstpage_image] =>[orig_patent_app_number] => 11415584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5167224 [patent_doc_number] => 20070288813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Cell board interconnection architecture with serviceable switch board' [patent_app_type] => utility [patent_app_number] => 11/414852 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288813.pdf [firstpage_image] =>[orig_patent_app_number] => 11414852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5036672 [patent_doc_number] => 20070101211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Defect management method and disk drive using the same' [patent_app_type] => utility [patent_app_number] => 11/412428 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3467 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101211.pdf [firstpage_image] =>[orig_patent_app_number] => 11412428 [rel_patent_id] =>[rel_patent_doc_number] =>)