Search

Elly Gerald Stoica

Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )

Most Active Art Unit
1647
Art Unit(s)
1647, 1646
Total Applications
1381
Issued Applications
805
Pending Applications
99
Abandoned Applications
477

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 396840 [patent_doc_number] => 07299387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Address generator for block interleaving' [patent_app_type] => utility [patent_app_number] => 10/971619 [patent_app_country] => US [patent_app_date] => 2004-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3788 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/299/07299387.pdf [firstpage_image] =>[orig_patent_app_number] => 10971619 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/971619
Address generator for block interleaving Oct 20, 2004 Issued
Array ( [id] => 7057423 [patent_doc_number] => 20050278598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Test apparatus' [patent_app_type] => utility [patent_app_number] => 10/933690 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13143 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278598.pdf [firstpage_image] =>[orig_patent_app_number] => 10933690 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/933690
Test apparatus for testing an electronic device Sep 2, 2004 Issued
Array ( [id] => 7085042 [patent_doc_number] => 20050050422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/926082 [patent_app_country] => US [patent_app_date] => 2004-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2890 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20050050422.pdf [firstpage_image] =>[orig_patent_app_number] => 10926082 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/926082
Semiconductor integrated circuit Aug 25, 2004 Abandoned
Array ( [id] => 5592345 [patent_doc_number] => 20060041798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Design techniques to increase testing efficiency' [patent_app_type] => utility [patent_app_number] => 10/922830 [patent_app_country] => US [patent_app_date] => 2004-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6480 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20060041798.pdf [firstpage_image] =>[orig_patent_app_number] => 10922830 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/922830
Design techniques to increase testing efficiency Aug 22, 2004 Abandoned
Array ( [id] => 898259 [patent_doc_number] => 07346817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems' [patent_app_type] => utility [patent_app_number] => 10/924306 [patent_app_country] => US [patent_app_date] => 2004-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2625 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346817.pdf [firstpage_image] =>[orig_patent_app_number] => 10924306 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/924306
Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems Aug 22, 2004 Issued
Array ( [id] => 5592350 [patent_doc_number] => 20060041803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Apparatus and method for dynamic in-circuit probing of field programmable gate arrays' [patent_app_type] => utility [patent_app_number] => 10/923460 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9770 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20060041803.pdf [firstpage_image] =>[orig_patent_app_number] => 10923460 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/923460
Apparatus and method for dynamic in-circuit probing of field programmable gate arrays Aug 19, 2004 Issued
Array ( [id] => 392998 [patent_doc_number] => 07302622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Integrated memory having a test circuit for functional testing of the memory' [patent_app_type] => utility [patent_app_number] => 10/920210 [patent_app_country] => US [patent_app_date] => 2004-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4844 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302622.pdf [firstpage_image] =>[orig_patent_app_number] => 10920210 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/920210
Integrated memory having a test circuit for functional testing of the memory Aug 17, 2004 Issued
Array ( [id] => 453503 [patent_doc_number] => 07251759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Method and apparatus to compare pointers associated with asynchronous clock domains' [patent_app_type] => utility [patent_app_number] => 10/918408 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6825 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/251/07251759.pdf [firstpage_image] =>[orig_patent_app_number] => 10918408 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918408
Method and apparatus to compare pointers associated with asynchronous clock domains Aug 15, 2004 Issued
Array ( [id] => 466177 [patent_doc_number] => 07243280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Semiconductor circuit apparatus and test method thereof' [patent_app_type] => utility [patent_app_number] => 10/918497 [patent_app_country] => US [patent_app_date] => 2004-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3270 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243280.pdf [firstpage_image] =>[orig_patent_app_number] => 10918497 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918497
Semiconductor circuit apparatus and test method thereof Aug 12, 2004 Issued
Array ( [id] => 508777 [patent_doc_number] => 07210087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Method and system for simulating a modular test system' [patent_app_type] => utility [patent_app_number] => 10/917711 [patent_app_country] => US [patent_app_date] => 2004-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8699 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/210/07210087.pdf [firstpage_image] =>[orig_patent_app_number] => 10917711 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917711
Method and system for simulating a modular test system Aug 12, 2004 Issued
Array ( [id] => 481619 [patent_doc_number] => 07228477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Apparatus and method for testing circuit units to be tested' [patent_app_type] => utility [patent_app_number] => 10/917176 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4105 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228477.pdf [firstpage_image] =>[orig_patent_app_number] => 10917176 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917176
Apparatus and method for testing circuit units to be tested Aug 11, 2004 Issued
Array ( [id] => 5803631 [patent_doc_number] => 20060036920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Built-in self-test (BIST) for high performance circuits' [patent_app_type] => utility [patent_app_number] => 10/915981 [patent_app_country] => US [patent_app_date] => 2004-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2195 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20060036920.pdf [firstpage_image] =>[orig_patent_app_number] => 10915981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915981
Built-in self-test (BIST) for high performance circuits Aug 10, 2004 Issued
Array ( [id] => 325271 [patent_doc_number] => 07519877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Memory with test mode output' [patent_app_type] => utility [patent_app_number] => 10/915663 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9520 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/519/07519877.pdf [firstpage_image] =>[orig_patent_app_number] => 10915663 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915663
Memory with test mode output Aug 9, 2004 Issued
Array ( [id] => 5774324 [patent_doc_number] => 20050268188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Backup method, backup system, disk controller and backup program' [patent_app_type] => utility [patent_app_number] => 10/910580 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4393 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20050268188.pdf [firstpage_image] =>[orig_patent_app_number] => 10910580 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/910580
Backup method, backup system, disk controller and backup program Aug 3, 2004 Issued
Array ( [id] => 7601877 [patent_doc_number] => 07237169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Cross-monitoring sensor system and method' [patent_app_type] => utility [patent_app_number] => 10/900028 [patent_app_country] => US [patent_app_date] => 2004-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4675 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/237/07237169.pdf [firstpage_image] =>[orig_patent_app_number] => 10900028 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/900028
Cross-monitoring sensor system and method Jul 25, 2004 Issued
Array ( [id] => 7262475 [patent_doc_number] => 20040260985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Synchronization of a communications system' [patent_app_type] => new [patent_app_number] => 10/893673 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7978 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20040260985.pdf [firstpage_image] =>[orig_patent_app_number] => 10893673 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/893673
Synchronization of a communications system Jul 14, 2004 Issued
Array ( [id] => 599365 [patent_doc_number] => 07444557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Memory with fault tolerant reference circuitry' [patent_app_type] => utility [patent_app_number] => 10/891649 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444557.pdf [firstpage_image] =>[orig_patent_app_number] => 10891649 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/891649
Memory with fault tolerant reference circuitry Jul 14, 2004 Issued
Array ( [id] => 7126333 [patent_doc_number] => 20050058077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Fast-path implementation for an uplink double tagging engine' [patent_app_type] => utility [patent_app_number] => 10/878677 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5872 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20050058077.pdf [firstpage_image] =>[orig_patent_app_number] => 10878677 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878677
Fast-path implementation for an uplink double tagging engine Jun 28, 2004 Abandoned
Array ( [id] => 469584 [patent_doc_number] => 07240254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Multiple power levels for a chip within a multi-chip semiconductor package' [patent_app_type] => utility [patent_app_number] => 10/877687 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7788 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240254.pdf [firstpage_image] =>[orig_patent_app_number] => 10877687 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877687
Multiple power levels for a chip within a multi-chip semiconductor package Jun 24, 2004 Issued
Array ( [id] => 8022805 [patent_doc_number] => 08140921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'System for elevator electronic safety device' [patent_app_type] => utility [patent_app_number] => 11/547635 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3836 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/140/08140921.pdf [firstpage_image] =>[orig_patent_app_number] => 11547635 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/547635
System for elevator electronic safety device Jun 21, 2004 Issued
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