Search

Elly Gerald Stoica

Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )

Most Active Art Unit
1647
Art Unit(s)
1647, 1646
Total Applications
1381
Issued Applications
805
Pending Applications
99
Abandoned Applications
477

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 882383 [patent_doc_number] => 07360133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Method for creating a JTAG tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool' [patent_app_type] => utility [patent_app_number] => 10/847691 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5198 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360133.pdf [firstpage_image] =>[orig_patent_app_number] => 10847691 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/847691
Method for creating a JTAG tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool May 17, 2004 Issued
Array ( [id] => 7241547 [patent_doc_number] => 20050257104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Method and apparatus for bit error rate test' [patent_app_type] => utility [patent_app_number] => 10/846469 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5685 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20050257104.pdf [firstpage_image] =>[orig_patent_app_number] => 10846469 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/846469
Method and apparatus for bit error rate test May 13, 2004 Abandoned
Array ( [id] => 498430 [patent_doc_number] => 07216270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-08 [patent_title] => 'System and method for providing testing and failure analysis of integrated circuit memory devices' [patent_app_type] => utility [patent_app_number] => 10/846004 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 6214 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/216/07216270.pdf [firstpage_image] =>[orig_patent_app_number] => 10846004 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/846004
System and method for providing testing and failure analysis of integrated circuit memory devices May 13, 2004 Issued
Array ( [id] => 7123704 [patent_doc_number] => 20050015533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Procedure and device for identifying an operating mode of a controlled device' [patent_app_type] => utility [patent_app_number] => 10/844978 [patent_app_country] => US [patent_app_date] => 2004-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9070 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20050015533.pdf [firstpage_image] =>[orig_patent_app_number] => 10844978 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/844978
Procedure and device for identifying an operating mode of a controlled device May 12, 2004 Issued
Array ( [id] => 7047121 [patent_doc_number] => 20050251716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Software to test a storage device connected to a high availability cluster of computers' [patent_app_type] => utility [patent_app_number] => 10/841171 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20050251716.pdf [firstpage_image] =>[orig_patent_app_number] => 10841171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/841171
Software to test a storage device connected to a high availability cluster of computers May 6, 2004 Abandoned
Array ( [id] => 519071 [patent_doc_number] => 07203875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Test systems and methods with compensation techniques' [patent_app_type] => utility [patent_app_number] => 10/841019 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 16828 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/203/07203875.pdf [firstpage_image] =>[orig_patent_app_number] => 10841019 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/841019
Test systems and methods with compensation techniques May 6, 2004 Issued
Array ( [id] => 7063500 [patent_doc_number] => 20050005215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Built-in self-test circuit for phase locked loops, test method and computer program product therefor' [patent_app_type] => utility [patent_app_number] => 10/841981 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3311 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20050005215.pdf [firstpage_image] =>[orig_patent_app_number] => 10841981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/841981
Built-in self-test circuit for phase locked loops, test method and computer program product therefor May 6, 2004 Issued
Array ( [id] => 7030833 [patent_doc_number] => 20050022080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Systems and methods associated with test equipment' [patent_app_type] => utility [patent_app_number] => 10/840898 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 17856 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20050022080.pdf [firstpage_image] =>[orig_patent_app_number] => 10840898 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/840898
Systems and methods associated with test equipment May 6, 2004 Issued
Array ( [id] => 5774321 [patent_doc_number] => 20050268186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Semiconductor wafer with test circuit and manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/841915 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2084 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20050268186.pdf [firstpage_image] =>[orig_patent_app_number] => 10841915 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/841915
Semiconductor wafer with test circuit and manufacturing method May 5, 2004 Abandoned
Array ( [id] => 7451511 [patent_doc_number] => 20040196709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Chip testing within a multi-chip semiconductor package' [patent_app_type] => new [patent_app_number] => 10/824734 [patent_app_country] => US [patent_app_date] => 2004-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6705 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20040196709.pdf [firstpage_image] =>[orig_patent_app_number] => 10824734 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/824734
Chip testing within a multi-chip semiconductor package Apr 14, 2004 Issued
Array ( [id] => 6953966 [patent_doc_number] => 20050229061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Method of efficiently compressing and decompressing test data using input reduction' [patent_app_type] => utility [patent_app_number] => 10/814127 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6040 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20050229061.pdf [firstpage_image] =>[orig_patent_app_number] => 10814127 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814127
Method of efficiently compressing and decompressing test data using input reduction Mar 31, 2004 Abandoned
Array ( [id] => 5650430 [patent_doc_number] => 20060136165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Boundary scan circuit with integrated sensor for sensing physical operating parameters' [patent_app_type] => utility [patent_app_number] => 10/544058 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4330 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20060136165.pdf [firstpage_image] =>[orig_patent_app_number] => 10544058 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/544058
Boundary scan circuit with integrated sensor for sensing physical operating parameters Dec 17, 2003 Issued
Array ( [id] => 7247254 [patent_doc_number] => 20040158782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Method for protected transmission of data via an air interface' [patent_app_type] => new [patent_app_number] => 10/722499 [patent_app_country] => US [patent_app_date] => 2003-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3581 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20040158782.pdf [firstpage_image] =>[orig_patent_app_number] => 10722499 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/722499
Method for protected transmission of data via an air interface Nov 27, 2003 Abandoned
Array ( [id] => 7246800 [patent_doc_number] => 20050073788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Integrated circuit outputs protection during JTAG board tests' [patent_app_type] => utility [patent_app_number] => 10/712660 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2043 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073788.pdf [firstpage_image] =>[orig_patent_app_number] => 10712660 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712660
Integrated circuit outputs protection during JTAG board tests Nov 12, 2003 Abandoned
Array ( [id] => 7608031 [patent_doc_number] => 07000169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Turbo decoding' [patent_app_type] => utility [patent_app_number] => 10/691078 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4970 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000169.pdf [firstpage_image] =>[orig_patent_app_number] => 10691078 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/691078
Turbo decoding Oct 20, 2003 Issued
Array ( [id] => 7246440 [patent_doc_number] => 20050081131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Correcting data having more data blocks with errors than redundancy blocks' [patent_app_type] => utility [patent_app_number] => 10/688027 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4599 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20050081131.pdf [firstpage_image] =>[orig_patent_app_number] => 10688027 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688027
Correcting data having more data blocks with errors than redundancy blocks Oct 16, 2003 Issued
Array ( [id] => 317039 [patent_doc_number] => 07526691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-28 [patent_title] => 'System and method for using TAP controllers' [patent_app_type] => utility [patent_app_number] => 10/686151 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2290 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/526/07526691.pdf [firstpage_image] =>[orig_patent_app_number] => 10686151 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/686151
System and method for using TAP controllers Oct 14, 2003 Issued
Array ( [id] => 423758 [patent_doc_number] => 07275188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-25 [patent_title] => 'Method and apparatus for burn-in of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/683205 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5751 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/275/07275188.pdf [firstpage_image] =>[orig_patent_app_number] => 10683205 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/683205
Method and apparatus for burn-in of semiconductor devices Oct 9, 2003 Issued
Array ( [id] => 7390007 [patent_doc_number] => 20040083077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Integrated packet bit error rate tester for 10G SERDES' [patent_app_type] => new [patent_app_number] => 10/681244 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9123 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20040083077.pdf [firstpage_image] =>[orig_patent_app_number] => 10681244 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/681244
Integrated packet bit error rate tester for 10G SERDES Oct 8, 2003 Issued
Array ( [id] => 905107 [patent_doc_number] => 07340660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Method and system for using statistical signatures for testing high-speed circuits' [patent_app_type] => utility [patent_app_number] => 10/680679 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4702 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340660.pdf [firstpage_image] =>[orig_patent_app_number] => 10680679 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/680679
Method and system for using statistical signatures for testing high-speed circuits Oct 6, 2003 Issued
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