Elly Gerald Stoica
Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )
Most Active Art Unit | 1647 |
Art Unit(s) | 1647, 1646 |
Total Applications | 1381 |
Issued Applications | 805 |
Pending Applications | 99 |
Abandoned Applications | 477 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 882383
[patent_doc_number] => 07360133
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-15
[patent_title] => 'Method for creating a JTAG tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool'
[patent_app_type] => utility
[patent_app_number] => 10/847691
[patent_app_country] => US
[patent_app_date] => 2004-05-18
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[pdf_file] => patents/07/360/07360133.pdf
[firstpage_image] =>[orig_patent_app_number] => 10847691
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/847691 | Method for creating a JTAG tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool | May 17, 2004 | Issued |
Array
(
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[patent_doc_number] => 20050257104
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[patent_issue_date] => 2005-11-17
[patent_title] => 'Method and apparatus for bit error rate test'
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[pdf_file] => publications/A1/0257/20050257104.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/846469 | Method and apparatus for bit error rate test | May 13, 2004 | Abandoned |
Array
(
[id] => 498430
[patent_doc_number] => 07216270
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-05-08
[patent_title] => 'System and method for providing testing and failure analysis of integrated circuit memory devices'
[patent_app_type] => utility
[patent_app_number] => 10/846004
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/846004 | System and method for providing testing and failure analysis of integrated circuit memory devices | May 13, 2004 | Issued |
Array
(
[id] => 7123704
[patent_doc_number] => 20050015533
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[patent_issue_date] => 2005-01-20
[patent_title] => 'Procedure and device for identifying an operating mode of a controlled device'
[patent_app_type] => utility
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Array
(
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[patent_title] => 'Software to test a storage device connected to a high availability cluster of computers'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/841171 | Software to test a storage device connected to a high availability cluster of computers | May 6, 2004 | Abandoned |
Array
(
[id] => 519071
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[patent_title] => 'Test systems and methods with compensation techniques'
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[firstpage_image] =>[orig_patent_app_number] => 10841019
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/841019 | Test systems and methods with compensation techniques | May 6, 2004 | Issued |
Array
(
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[patent_title] => 'Built-in self-test circuit for phase locked loops, test method and computer program product therefor'
[patent_app_type] => utility
[patent_app_number] => 10/841981
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[firstpage_image] =>[orig_patent_app_number] => 10841981
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/841981 | Built-in self-test circuit for phase locked loops, test method and computer program product therefor | May 6, 2004 | Issued |
Array
(
[id] => 7030833
[patent_doc_number] => 20050022080
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[patent_issue_date] => 2005-01-27
[patent_title] => 'Systems and methods associated with test equipment'
[patent_app_type] => utility
[patent_app_number] => 10/840898
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[pdf_file] => publications/A1/0022/20050022080.pdf
[firstpage_image] =>[orig_patent_app_number] => 10840898
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/840898 | Systems and methods associated with test equipment | May 6, 2004 | Issued |
Array
(
[id] => 5774321
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[patent_title] => 'Semiconductor wafer with test circuit and manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 10/841915
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[firstpage_image] =>[orig_patent_app_number] => 10841915
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/841915 | Semiconductor wafer with test circuit and manufacturing method | May 5, 2004 | Abandoned |
Array
(
[id] => 7451511
[patent_doc_number] => 20040196709
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[patent_issue_date] => 2004-10-07
[patent_title] => 'Chip testing within a multi-chip semiconductor package'
[patent_app_type] => new
[patent_app_number] => 10/824734
[patent_app_country] => US
[patent_app_date] => 2004-04-15
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Array
(
[id] => 6953966
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[patent_title] => 'Method of efficiently compressing and decompressing test data using input reduction'
[patent_app_type] => utility
[patent_app_number] => 10/814127
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/814127 | Method of efficiently compressing and decompressing test data using input reduction | Mar 31, 2004 | Abandoned |
Array
(
[id] => 5650430
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[patent_title] => 'Boundary scan circuit with integrated sensor for sensing physical operating parameters'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/544058 | Boundary scan circuit with integrated sensor for sensing physical operating parameters | Dec 17, 2003 | Issued |
Array
(
[id] => 7247254
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[patent_title] => 'Method for protected transmission of data via an air interface'
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Array
(
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[patent_title] => 'Integrated circuit outputs protection during JTAG board tests'
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Array
(
[id] => 7608031
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Array
(
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/680679 | Method and system for using statistical signatures for testing high-speed circuits | Oct 6, 2003 | Issued |