Elly Gerald Stoica

Array ( [id] => 248888 [patent_doc_number] => 07587649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Testing of reconfigurable logic and interconnect sources' [patent_app_type] => utility [patent_app_number] => 10/673211 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 7323 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/587/07587649.pdf [firstpage_image] =>[orig_patent_app_number] => 10673211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 379133 [patent_doc_number] => 07313743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Hybrid scan-based delay testing technique for compact and high fault coverage test set' [patent_app_type] => utility [patent_app_number] => 10/653959 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6990 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313743.pdf [firstpage_image] =>[orig_patent_app_number] => 10653959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 877802 [patent_doc_number] => 07363567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'System and method for electronic device testing using random parameter looping' [patent_app_type] => utility [patent_app_number] => 10/650957 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3911 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/363/07363567.pdf [firstpage_image] =>[orig_patent_app_number] => 10650957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7676026 [patent_doc_number] => 20040153801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Semiconductor integrated circuit and method for testing same' [patent_app_type] => new [patent_app_number] => 10/647217 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5126 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153801.pdf [firstpage_image] =>[orig_patent_app_number] => 10647217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 423756 [patent_doc_number] => 07275187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Test circuit for memory' [patent_app_type] => utility [patent_app_number] => 10/646868 [patent_app_country] => US [patent_app_date] => 2003-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5101 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/275/07275187.pdf [firstpage_image] =>[orig_patent_app_number] => 10646868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 388753 [patent_doc_number] => 07305597 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-04 [patent_title] => 'System and method for efficiently testing a large random access memory space' [patent_app_type] => utility [patent_app_number] => 10/646535 [patent_app_country] => US [patent_app_date] => 2003-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305597.pdf [firstpage_image] =>[orig_patent_app_number] => 10646535 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7247266 [patent_doc_number] => 20040158784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Microprocessor based self-diagnostic port' [patent_app_type] => new [patent_app_number] => 10/647018 [patent_app_country] => US [patent_app_date] => 2003-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20040158784.pdf [firstpage_image] =>[orig_patent_app_number] => 10647018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 649121 [patent_doc_number] => 07120839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'High-accuracy continuous duty-cycle correction circuit' [patent_app_type] => utility [patent_app_number] => 10/645660 [patent_app_country] => US [patent_app_date] => 2003-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4271 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120839.pdf [firstpage_image] =>[orig_patent_app_number] => 10645660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7215279 [patent_doc_number] => 20050044460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Mapping test mux structure' [patent_app_type] => utility [patent_app_number] => 10/646010 [patent_app_country] => US [patent_app_date] => 2003-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2674 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20050044460.pdf [firstpage_image] =>[orig_patent_app_number] => 10646010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7215295 [patent_doc_number] => 20050044463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Programmable jitter generator' [patent_app_type] => utility [patent_app_number] => 10/646957 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4939 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20050044463.pdf [firstpage_image] =>[orig_patent_app_number] => 10646957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 494092 [patent_doc_number] => 07219273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Method for testing media in a library without inserting media into the library database' [patent_app_type] => utility [patent_app_number] => 10/644209 [patent_app_country] => US [patent_app_date] => 2003-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/219/07219273.pdf [firstpage_image] =>[orig_patent_app_number] => 10644209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7196094 [patent_doc_number] => 20050041460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Method and circuit for scan testing latch based random access memory' [patent_app_type] => utility [patent_app_number] => 10/645900 [patent_app_country] => US [patent_app_date] => 2003-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5528 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20050041460.pdf [firstpage_image] =>[orig_patent_app_number] => 10645900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 375012 [patent_doc_number] => 07475320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components' [patent_app_type] => utility [patent_app_number] => 10/643549 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5752 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475320.pdf [firstpage_image] =>[orig_patent_app_number] => 10643549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 598939 [patent_doc_number] => 07447960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Method of efficiently loading scan and non-scan memory elements' [patent_app_type] => utility [patent_app_number] => 10/636984 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1831 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/447/07447960.pdf [firstpage_image] =>[orig_patent_app_number] => 10636984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7417868 [patent_doc_number] => 20040107396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Built-in self test circuit for integrated circuits' [patent_app_type] => new [patent_app_number] => 10/638284 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10085 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20040107396.pdf [firstpage_image] =>[orig_patent_app_number] => 10638284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5741584 [patent_doc_number] => 20060087307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Single pin multilevel integrated circuit test interface' [patent_app_type] => utility [patent_app_number] => 10/519346 [patent_app_country] => US [patent_app_date] => 2003-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1956 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20060087307.pdf [firstpage_image] =>[orig_patent_app_number] => 10519346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 379120 [patent_doc_number] => 07313737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Adaptive link adaptation' [patent_app_type] => utility [patent_app_number] => 10/434476 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3497 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313737.pdf [firstpage_image] =>[orig_patent_app_number] => 10434476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7392199 [patent_doc_number] => 20040083419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Detection circuit and decoding circuit' [patent_app_type] => new [patent_app_number] => 10/431459 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10790 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20040083419.pdf [firstpage_image] =>[orig_patent_app_number] => 10431459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6824540 [patent_doc_number] => 20030235162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Method and apparatus for reducing transmission errors in a third generation cellular system' [patent_app_type] => new [patent_app_number] => 10/431089 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4315 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20030235162.pdf [firstpage_image] =>[orig_patent_app_number] => 10431089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 490520 [patent_doc_number] => 07222272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Semiconductor integrated circuit and testing method thereof' [patent_app_type] => utility [patent_app_number] => 10/430319 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7378 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/222/07222272.pdf [firstpage_image] =>[orig_patent_app_number] => 10430319 [rel_patent_id] =>[rel_patent_doc_number] =>)