Elly Gerald Stoica
Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )
Most Active Art Unit | 1647 |
Art Unit(s) | 1647, 1646 |
Total Applications | 1381 |
Issued Applications | 805 |
Pending Applications | 99 |
Abandoned Applications | 477 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 14966871
[patent_doc_number] => 20190310914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-10
[patent_title] => BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF10/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
[patent_app_type] => utility
[patent_app_number] => 16/436748
[patent_app_country] => US
[patent_app_date] => 2019-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5368
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16436748
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/436748 | Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 10/15 and 256-symbol mapping, and bit interleaving method using same | Jun 9, 2019 | Issued |
Array
(
[id] => 14872563
[patent_doc_number] => 20190286523
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-19
[patent_title] => MANAGING DATA STORAGE
[patent_app_type] => utility
[patent_app_number] => 16/432680
[patent_app_country] => US
[patent_app_date] => 2019-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6275
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432680
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/432680 | Managing data storage | Jun 4, 2019 | Issued |
Array
(
[id] => 16537314
[patent_doc_number] => 10879935
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-29
[patent_title] => LDPC decoder, semiconductor memory system, and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 16/424954
[patent_app_country] => US
[patent_app_date] => 2019-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 21
[patent_no_of_words] => 18566
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424954
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/424954 | LDPC decoder, semiconductor memory system, and operating method thereof | May 28, 2019 | Issued |
Array
(
[id] => 16472501
[patent_doc_number] => 20200374039
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-26
[patent_title] => PACKET REPLAY IN RESPONSE TO CHECKSUM ERROR
[patent_app_type] => utility
[patent_app_number] => 16/422950
[patent_app_country] => US
[patent_app_date] => 2019-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6903
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422950
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/422950 | Packet replay in response to checksum error | May 23, 2019 | Issued |
Array
(
[id] => 16737675
[patent_doc_number] => 10963327
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-30
[patent_title] => Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management
[patent_app_type] => utility
[patent_app_number] => 16/417453
[patent_app_country] => US
[patent_app_date] => 2019-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 8569
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417453
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/417453 | Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management | May 19, 2019 | Issued |
Array
(
[id] => 18416568
[patent_doc_number] => 11671119
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-06
[patent_title] => Signal processing apparatus and signal processing method
[patent_app_type] => utility
[patent_app_number] => 17/056719
[patent_app_country] => US
[patent_app_date] => 2019-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 10403
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17056719
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/056719 | Signal processing apparatus and signal processing method | May 8, 2019 | Issued |
Array
(
[id] => 14780797
[patent_doc_number] => 20190265296
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => IMPORTANCE SAMPLING METHOD FOR MULTIPLE FAILURE REGIONS
[patent_app_type] => utility
[patent_app_number] => 16/406868
[patent_app_country] => US
[patent_app_date] => 2019-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6488
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406868
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/406868 | Importance sampling method for multiple failure regions | May 7, 2019 | Issued |
Array
(
[id] => 16667170
[patent_doc_number] => 10936416
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-02
[patent_title] => Redundant array of independent NAND for a three-dimensional memory array
[patent_app_type] => utility
[patent_app_number] => 16/402481
[patent_app_country] => US
[patent_app_date] => 2019-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 5
[patent_no_of_words] => 7163
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402481
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/402481 | Redundant array of independent NAND for a three-dimensional memory array | May 2, 2019 | Issued |
Array
(
[id] => 14689191
[patent_doc_number] => 20190243711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => FOCUSED STORAGE POOL EXPANSION TO PREVENT A PERFORMANCE DEGRADATION
[patent_app_type] => utility
[patent_app_number] => 16/390679
[patent_app_country] => US
[patent_app_date] => 2019-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10765
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 381
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390679
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/390679 | Focused storage pool expansion to prevent a performance degradation | Apr 21, 2019 | Issued |
Array
(
[id] => 17211348
[patent_doc_number] => 11171738
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-09
[patent_title] => Enhanced automatic identification system
[patent_app_type] => utility
[patent_app_number] => 16/390404
[patent_app_country] => US
[patent_app_date] => 2019-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 11725
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390404
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/390404 | Enhanced automatic identification system | Apr 21, 2019 | Issued |
Array
(
[id] => 17364970
[patent_doc_number] => 11231991
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-25
[patent_title] => System on chip and memory system including security processor with improved memory use efficiency and method of operating system on chip
[patent_app_type] => utility
[patent_app_number] => 16/388192
[patent_app_country] => US
[patent_app_date] => 2019-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 11169
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16388192
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/388192 | System on chip and memory system including security processor with improved memory use efficiency and method of operating system on chip | Apr 17, 2019 | Issued |
Array
(
[id] => 15028663
[patent_doc_number] => 20190325336
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => QUANTUM BIOS FOR RECONFIGURING QUANTUM COMPUTING ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 16/388283
[patent_app_country] => US
[patent_app_date] => 2019-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5096
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16388283
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/388283 | Quantum bios for reconfiguring quantum computing architectures | Apr 17, 2019 | Issued |
Array
(
[id] => 16864578
[patent_doc_number] => 11023320
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Technologies for providing multiple levels of error correction
[patent_app_type] => utility
[patent_app_number] => 16/375362
[patent_app_country] => US
[patent_app_date] => 2019-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6637
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16375362
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/375362 | Technologies for providing multiple levels of error correction | Apr 3, 2019 | Issued |
Array
(
[id] => 16346260
[patent_doc_number] => 20200310911
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => SYSTEMS AND METHODS FOR AN ECC ARCHITECTURE WITH PRIORITIZED TASK QUEUES
[patent_app_type] => utility
[patent_app_number] => 16/364360
[patent_app_country] => US
[patent_app_date] => 2019-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6452
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364360
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/364360 | Systems and methods for an ECC architecture with prioritized task queues | Mar 25, 2019 | Issued |
Array
(
[id] => 16801340
[patent_doc_number] => 10996273
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-04
[patent_title] => Test generation using testability-based guidance
[patent_app_type] => utility
[patent_app_number] => 16/360419
[patent_app_country] => US
[patent_app_date] => 2019-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 9651
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16360419
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/360419 | Test generation using testability-based guidance | Mar 20, 2019 | Issued |
Array
(
[id] => 15685393
[patent_doc_number] => 20200097360
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => SYSTEM AND METHOD OF REDUCING LOGIC FOR MULTI-BIT ERROR CORRECTING CODES
[patent_app_type] => utility
[patent_app_number] => 16/285677
[patent_app_country] => US
[patent_app_date] => 2019-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6474
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16285677
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/285677 | System and method of reducing logic for multi-bit error correcting codes | Feb 25, 2019 | Issued |
Array
(
[id] => 17076063
[patent_doc_number] => 11112455
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-07
[patent_title] => Built-in self-test circuits and related methods
[patent_app_type] => utility
[patent_app_number] => 16/286413
[patent_app_country] => US
[patent_app_date] => 2019-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 19099
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286413
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/286413 | Built-in self-test circuits and related methods | Feb 25, 2019 | Issued |
Array
(
[id] => 16478239
[patent_doc_number] => 10853187
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-01
[patent_title] => Joint de-duplication-erasure coded distributed storage
[patent_app_type] => utility
[patent_app_number] => 16/285320
[patent_app_country] => US
[patent_app_date] => 2019-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 14027
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16285320
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/285320 | Joint de-duplication-erasure coded distributed storage | Feb 25, 2019 | Issued |
Array
(
[id] => 15499157
[patent_doc_number] => 20200049767
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-13
[patent_title] => SEMICONDUCTOR DEVICES INCLUDING STACKED DIES AND METHODS OF TESTING THE SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/285599
[patent_app_country] => US
[patent_app_date] => 2019-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7226
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16285599
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/285599 | SEMICONDUCTOR DEVICES INCLUDING STACKED DIES AND METHODS OF TESTING THE SEMICONDUCTOR DEVICES | Feb 25, 2019 | Abandoned |
Array
(
[id] => 14415547
[patent_doc_number] => 20190173617
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-06
[patent_title] => ITERATIVE MULTI-LEVEL EQUALIZATION AND DECODING
[patent_app_type] => utility
[patent_app_number] => 16/273649
[patent_app_country] => US
[patent_app_date] => 2019-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3548
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16273649
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/273649 | ITERATIVE MULTI-LEVEL EQUALIZATION AND DECODING | Feb 11, 2019 | Abandoned |