Search

Elly Gerald Stoica

Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )

Most Active Art Unit
1647
Art Unit(s)
1647, 1646
Total Applications
1381
Issued Applications
805
Pending Applications
99
Abandoned Applications
477

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6707705 [patent_doc_number] => 20030154439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Code generator circuit' [patent_app_type] => new [patent_app_number] => 10/329341 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5044 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20030154439.pdf [firstpage_image] =>[orig_patent_app_number] => 10329341 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329341
Code generator circuit Dec 26, 2002 Abandoned
Array ( [id] => 6844566 [patent_doc_number] => 20030149913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Method and apparatus for efficient burn-in of electronic circuits' [patent_app_type] => new [patent_app_number] => 10/330502 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20030149913.pdf [firstpage_image] =>[orig_patent_app_number] => 10330502 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/330502
Method and apparatus for efficient burn-in of electronic circuits Dec 26, 2002 Abandoned
Array ( [id] => 7673508 [patent_doc_number] => 20040128610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Method and apparatus for using multi-dimensional trellis codes over multi-path channels' [patent_app_type] => new [patent_app_number] => 10/329896 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8915 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128610.pdf [firstpage_image] =>[orig_patent_app_number] => 10329896 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329896
Method and apparatus for using multi-dimensional trellis codes over multi-path channels Dec 25, 2002 Issued
Array ( [id] => 7316269 [patent_doc_number] => 20040034828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Hardware-efficient low density parity check code for digital communications' [patent_app_type] => new [patent_app_number] => 10/329597 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19909 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20040034828.pdf [firstpage_image] =>[orig_patent_app_number] => 10329597 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329597
Hardware-efficient low density parity check code for digital communications Dec 25, 2002 Issued
Array ( [id] => 7673527 [patent_doc_number] => 20040128591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'On-chip jitter testing' [patent_app_type] => new [patent_app_number] => 10/331122 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1146 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128591.pdf [firstpage_image] =>[orig_patent_app_number] => 10331122 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331122
On-chip jitter testing Dec 25, 2002 Issued
Array ( [id] => 6822986 [patent_doc_number] => 20030221147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Compression test circuit' [patent_app_type] => new [patent_app_number] => 10/329961 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4760 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20030221147.pdf [firstpage_image] =>[orig_patent_app_number] => 10329961 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329961
Compression test circuit Dec 25, 2002 Abandoned
Array ( [id] => 7675916 [patent_doc_number] => 20040153911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Testing of a CAM' [patent_app_type] => new [patent_app_number] => 10/327045 [patent_app_country] => US [patent_app_date] => 2002-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8417 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153911.pdf [firstpage_image] =>[orig_patent_app_number] => 10327045 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327045
Testing of a CAM Dec 23, 2002 Abandoned
Array ( [id] => 757998 [patent_doc_number] => 07024614 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'Disk drive employing a configuration data structure comprising a plurality of configuration parameters to facilitate disk commands' [patent_app_type] => utility [patent_app_number] => 10/329155 [patent_app_country] => US [patent_app_date] => 2002-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6861 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024614.pdf [firstpage_image] =>[orig_patent_app_number] => 10329155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329155
Disk drive employing a configuration data structure comprising a plurality of configuration parameters to facilitate disk commands Dec 23, 2002 Issued
Array ( [id] => 691066 [patent_doc_number] => 07080305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'System and method for correcting data errors' [patent_app_type] => utility [patent_app_number] => 10/327729 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4675 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080305.pdf [firstpage_image] =>[orig_patent_app_number] => 10327729 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327729
System and method for correcting data errors Dec 22, 2002 Issued
Array ( [id] => 6798562 [patent_doc_number] => 20030177437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Erroneous packet data convergence protocol data unit handling scheme in a wireless communication system' [patent_app_type] => new [patent_app_number] => 10/325948 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20030177437.pdf [firstpage_image] =>[orig_patent_app_number] => 10325948 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/325948
Erroneous packet data convergence protocol data unit handling scheme in a wireless communication system Dec 22, 2002 Abandoned
Array ( [id] => 787732 [patent_doc_number] => 06990621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Enabling at speed application of test patterns associated with a wide tester interface on a low pin count tester' [patent_app_type] => utility [patent_app_number] => 10/326723 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3368 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990621.pdf [firstpage_image] =>[orig_patent_app_number] => 10326723 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/326723
Enabling at speed application of test patterns associated with a wide tester interface on a low pin count tester Dec 19, 2002 Issued
Array ( [id] => 535509 [patent_doc_number] => 07194673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Detecting intermittent losses of synchronization in a fibre channel loop' [patent_app_type] => utility [patent_app_number] => 10/327338 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194673.pdf [firstpage_image] =>[orig_patent_app_number] => 10327338 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327338
Detecting intermittent losses of synchronization in a fibre channel loop Dec 19, 2002 Issued
Array ( [id] => 7675937 [patent_doc_number] => 20040153890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Delay management system' [patent_app_type] => new [patent_app_number] => 10/327386 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153890.pdf [firstpage_image] =>[orig_patent_app_number] => 10327386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327386
Delay management system Dec 19, 2002 Issued
Array ( [id] => 7309448 [patent_doc_number] => 20040117703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Stimulus generation' [patent_app_type] => new [patent_app_number] => 10/317605 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5668 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20040117703.pdf [firstpage_image] =>[orig_patent_app_number] => 10317605 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/317605
Stimulus generation Dec 10, 2002 Issued
Array ( [id] => 765527 [patent_doc_number] => 07017094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Performance built-in self test system for a device and a method of use' [patent_app_type] => utility [patent_app_number] => 10/304246 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4563 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/017/07017094.pdf [firstpage_image] =>[orig_patent_app_number] => 10304246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/304246
Performance built-in self test system for a device and a method of use Nov 25, 2002 Issued
Array ( [id] => 685544 [patent_doc_number] => 07082558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Increasing possible test patterns which can be used with sequential scanning techniques to perform speed analysis' [patent_app_type] => utility [patent_app_number] => 10/302886 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/082/07082558.pdf [firstpage_image] =>[orig_patent_app_number] => 10302886 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302886
Increasing possible test patterns which can be used with sequential scanning techniques to perform speed analysis Nov 24, 2002 Issued
Array ( [id] => 388747 [patent_doc_number] => 07305594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Integrated circuit in a maximum input/output configuration' [patent_app_type] => utility [patent_app_number] => 10/303179 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1713 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305594.pdf [firstpage_image] =>[orig_patent_app_number] => 10303179 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303179
Integrated circuit in a maximum input/output configuration Nov 24, 2002 Issued
Array ( [id] => 7675932 [patent_doc_number] => 20040153895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Imprecise detection of triggers and trigger ordering for asynchronous events' [patent_app_type] => new [patent_app_number] => 10/302451 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4040 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153895.pdf [firstpage_image] =>[orig_patent_app_number] => 10302451 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302451
Imprecise detection of triggers and trigger ordering for asynchronous events Nov 21, 2002 Abandoned
Array ( [id] => 619866 [patent_doc_number] => 07146553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Error correction improvement for concatenated codes' [patent_app_type] => utility [patent_app_number] => 10/301769 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4578 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/146/07146553.pdf [firstpage_image] =>[orig_patent_app_number] => 10301769 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301769
Error correction improvement for concatenated codes Nov 19, 2002 Issued
Array ( [id] => 404292 [patent_doc_number] => 07293207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-06 [patent_title] => 'Method for testing memory in a computer system utilizing a CPU with either 32-bit or 36-bit memory addressing' [patent_app_type] => utility [patent_app_number] => 10/263391 [patent_app_country] => US [patent_app_date] => 2002-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/293/07293207.pdf [firstpage_image] =>[orig_patent_app_number] => 10263391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263391
Method for testing memory in a computer system utilizing a CPU with either 32-bit or 36-bit memory addressing Oct 1, 2002 Issued
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