Search

Elly Gerald Stoica

Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )

Most Active Art Unit
1647
Art Unit(s)
1647, 1646
Total Applications
1381
Issued Applications
805
Pending Applications
99
Abandoned Applications
477

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6226884 [patent_doc_number] => 20020004923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Integrated circuit' [patent_app_type] => new [patent_app_number] => 09/736328 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9053 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004923.pdf [firstpage_image] =>[orig_patent_app_number] => 09736328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736328
Integrated circuit Dec 14, 2000 Issued
Array ( [id] => 7105732 [patent_doc_number] => 20010004760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'Chip testing apparatus and method' [patent_app_type] => new-utility [patent_app_number] => 09/734600 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004760.pdf [firstpage_image] =>[orig_patent_app_number] => 09734600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734600
Chip testing apparatus and method Dec 12, 2000 Issued
Array ( [id] => 5990869 [patent_doc_number] => 20020099985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Methods of estimating error rates for communications received using iterative processing and related receivers' [patent_app_type] => new [patent_app_number] => 09/736761 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5400 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099985.pdf [firstpage_image] =>[orig_patent_app_number] => 09736761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736761
Methods of estimating error rates for communications received using iterative processing and related receivers Dec 12, 2000 Issued
Array ( [id] => 7609988 [patent_doc_number] => 06842871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Encoding method and device, decoding method and device, and systems using them' [patent_app_type] => utility [patent_app_number] => 09/733965 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10908 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842871.pdf [firstpage_image] =>[orig_patent_app_number] => 09733965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733965
Encoding method and device, decoding method and device, and systems using them Dec 11, 2000 Issued
Array ( [id] => 1240989 [patent_doc_number] => 06691272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Testing of high speed DDR interface using single clock edge triggered tester data' [patent_app_type] => B2 [patent_app_number] => 09/735820 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1369 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691272.pdf [firstpage_image] =>[orig_patent_app_number] => 09735820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735820
Testing of high speed DDR interface using single clock edge triggered tester data Dec 11, 2000 Issued
Array ( [id] => 1170586 [patent_doc_number] => 06766485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Integrated circuit fault tester, integrated circuit fault test method and recording medium recorded with fault test control program' [patent_app_type] => B1 [patent_app_number] => 09/669113 [patent_app_country] => US [patent_app_date] => 2000-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4561 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766485.pdf [firstpage_image] =>[orig_patent_app_number] => 09669113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/669113
Integrated circuit fault tester, integrated circuit fault test method and recording medium recorded with fault test control program Sep 24, 2000 Issued
Array ( [id] => 1234623 [patent_doc_number] => 06697995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Diagnostic method for logic used in vehicle' [patent_app_type] => B1 [patent_app_number] => 09/667595 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2484 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697995.pdf [firstpage_image] =>[orig_patent_app_number] => 09667595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667595
Diagnostic method for logic used in vehicle Sep 21, 2000 Issued
Array ( [id] => 1197135 [patent_doc_number] => 06732304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Chip testing within a multi-chip semiconductor package' [patent_app_type] => B1 [patent_app_number] => 09/666208 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6639 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732304.pdf [firstpage_image] =>[orig_patent_app_number] => 09666208 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/666208
Chip testing within a multi-chip semiconductor package Sep 20, 2000 Issued
09/668059 Turbo decoding Sep 19, 2000 Abandoned
Array ( [id] => 1201123 [patent_doc_number] => 06728910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Memory testing for built-in self-repair system' [patent_app_type] => B1 [patent_app_number] => 09/665749 [patent_app_country] => US [patent_app_date] => 2000-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6334 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728910.pdf [firstpage_image] =>[orig_patent_app_number] => 09665749 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/665749
Memory testing for built-in self-repair system Sep 19, 2000 Issued
Array ( [id] => 7631509 [patent_doc_number] => 06665828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Globally distributed scan blocks' [patent_app_type] => B1 [patent_app_number] => 09/664848 [patent_app_country] => US [patent_app_date] => 2000-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5291 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665828.pdf [firstpage_image] =>[orig_patent_app_number] => 09664848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/664848
Globally distributed scan blocks Sep 18, 2000 Issued
Array ( [id] => 984761 [patent_doc_number] => 06928593 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-09 [patent_title] => 'Memory module and memory component built-in self test' [patent_app_type] => utility [patent_app_number] => 09/664910 [patent_app_country] => US [patent_app_date] => 2000-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1852 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928593.pdf [firstpage_image] =>[orig_patent_app_number] => 09664910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/664910
Memory module and memory component built-in self test Sep 17, 2000 Issued
Array ( [id] => 1110004 [patent_doc_number] => 06813743 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Sliding window technique for map decoders' [patent_app_type] => B1 [patent_app_number] => 09/629122 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5525 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813743.pdf [firstpage_image] =>[orig_patent_app_number] => 09629122 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/629122
Sliding window technique for map decoders Jul 30, 2000 Issued
Array ( [id] => 1192672 [patent_doc_number] => 06735728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Unidirectional verification of bus-based systems' [patent_app_type] => B1 [patent_app_number] => 09/626290 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4892 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735728.pdf [firstpage_image] =>[orig_patent_app_number] => 09626290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626290
Unidirectional verification of bus-based systems Jul 24, 2000 Issued
Array ( [id] => 1186728 [patent_doc_number] => 06738935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Coding sublayer for multi-channel media with error correction' [patent_app_type] => B1 [patent_app_number] => 09/626275 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 14043 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738935.pdf [firstpage_image] =>[orig_patent_app_number] => 09626275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626275
Coding sublayer for multi-channel media with error correction Jul 24, 2000 Issued
Array ( [id] => 1207009 [patent_doc_number] => 06721911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Method and apparatus for testing a memory array using compressed responses' [patent_app_type] => B1 [patent_app_number] => 09/624476 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3403 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721911.pdf [firstpage_image] =>[orig_patent_app_number] => 09624476 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624476
Method and apparatus for testing a memory array using compressed responses Jul 23, 2000 Issued
Array ( [id] => 1234553 [patent_doc_number] => 06697978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Method for testing of known good die' [patent_app_type] => B1 [patent_app_number] => 09/624247 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6030 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697978.pdf [firstpage_image] =>[orig_patent_app_number] => 09624247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624247
Method for testing of known good die Jul 23, 2000 Issued
Array ( [id] => 1218309 [patent_doc_number] => 06711705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method of analyzing a relief of failure cell in a memory and memory testing apparatus having a failure relief analyzer using the method' [patent_app_type] => B1 [patent_app_number] => 09/621326 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 12751 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711705.pdf [firstpage_image] =>[orig_patent_app_number] => 09621326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/621326
Method of analyzing a relief of failure cell in a memory and memory testing apparatus having a failure relief analyzer using the method Jul 20, 2000 Issued
Array ( [id] => 1184993 [patent_doc_number] => 06748566 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Ensuring proper acceptance of data at a receiver in wireless multiple access communications systems' [patent_app_type] => B1 [patent_app_number] => 09/620797 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3960 [patent_no_of_claims] => 107 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748566.pdf [firstpage_image] =>[orig_patent_app_number] => 09620797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/620797
Ensuring proper acceptance of data at a receiver in wireless multiple access communications systems Jul 20, 2000 Issued
Array ( [id] => 1407865 [patent_doc_number] => 06560745 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method of identifying boundary of markerless codeword' [patent_app_type] => B1 [patent_app_number] => 09/626364 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 7581 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560745.pdf [firstpage_image] =>[orig_patent_app_number] => 09626364 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626364
Method of identifying boundary of markerless codeword Jul 20, 2000 Issued
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