Elly Gerald Stoica
Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )
Most Active Art Unit | 1647 |
Art Unit(s) | 1647, 1646 |
Total Applications | 1381 |
Issued Applications | 805 |
Pending Applications | 99 |
Abandoned Applications | 477 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6226884
[patent_doc_number] => 20020004923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-10
[patent_title] => 'Integrated circuit'
[patent_app_type] => new
[patent_app_number] => 09/736328
[patent_app_country] => US
[patent_app_date] => 2000-12-15
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[pdf_file] => publications/A1/0004/20020004923.pdf
[firstpage_image] =>[orig_patent_app_number] => 09736328
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/736328 | Integrated circuit | Dec 14, 2000 | Issued |
Array
(
[id] => 7105732
[patent_doc_number] => 20010004760
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[patent_kind] => A1
[patent_issue_date] => 2001-06-21
[patent_title] => 'Chip testing apparatus and method'
[patent_app_type] => new-utility
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/734600 | Chip testing apparatus and method | Dec 12, 2000 | Issued |
Array
(
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[patent_doc_number] => 20020099985
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[patent_kind] => A1
[patent_issue_date] => 2002-07-25
[patent_title] => 'Methods of estimating error rates for communications received using iterative processing and related receivers'
[patent_app_type] => new
[patent_app_number] => 09/736761
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[patent_app_date] => 2000-12-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/736761 | Methods of estimating error rates for communications received using iterative processing and related receivers | Dec 12, 2000 | Issued |
Array
(
[id] => 7609988
[patent_doc_number] => 06842871
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-11
[patent_title] => 'Encoding method and device, decoding method and device, and systems using them'
[patent_app_type] => utility
[patent_app_number] => 09/733965
[patent_app_country] => US
[patent_app_date] => 2000-12-12
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[firstpage_image] =>[orig_patent_app_number] => 09733965
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/733965 | Encoding method and device, decoding method and device, and systems using them | Dec 11, 2000 | Issued |
Array
(
[id] => 1240989
[patent_doc_number] => 06691272
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[patent_issue_date] => 2004-02-10
[patent_title] => 'Testing of high speed DDR interface using single clock edge triggered tester data'
[patent_app_type] => B2
[patent_app_number] => 09/735820
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Array
(
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[patent_issue_date] => 2004-07-20
[patent_title] => 'Integrated circuit fault tester, integrated circuit fault test method and recording medium recorded with fault test control program'
[patent_app_type] => B1
[patent_app_number] => 09/669113
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/669113 | Integrated circuit fault tester, integrated circuit fault test method and recording medium recorded with fault test control program | Sep 24, 2000 | Issued |
Array
(
[id] => 1234623
[patent_doc_number] => 06697995
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-24
[patent_title] => 'Diagnostic method for logic used in vehicle'
[patent_app_type] => B1
[patent_app_number] => 09/667595
[patent_app_country] => US
[patent_app_date] => 2000-09-22
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[pdf_file] => patents/06/697/06697995.pdf
[firstpage_image] =>[orig_patent_app_number] => 09667595
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/667595 | Diagnostic method for logic used in vehicle | Sep 21, 2000 | Issued |
Array
(
[id] => 1197135
[patent_doc_number] => 06732304
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-05-04
[patent_title] => 'Chip testing within a multi-chip semiconductor package'
[patent_app_type] => B1
[patent_app_number] => 09/666208
[patent_app_country] => US
[patent_app_date] => 2000-09-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/732/06732304.pdf
[firstpage_image] =>[orig_patent_app_number] => 09666208
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/666208 | Chip testing within a multi-chip semiconductor package | Sep 20, 2000 | Issued |
09/668059 | Turbo decoding | Sep 19, 2000 | Abandoned |
Array
(
[id] => 1201123
[patent_doc_number] => 06728910
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-27
[patent_title] => 'Memory testing for built-in self-repair system'
[patent_app_type] => B1
[patent_app_number] => 09/665749
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/665749 | Memory testing for built-in self-repair system | Sep 19, 2000 | Issued |
Array
(
[id] => 7631509
[patent_doc_number] => 06665828
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-16
[patent_title] => 'Globally distributed scan blocks'
[patent_app_type] => B1
[patent_app_number] => 09/664848
[patent_app_country] => US
[patent_app_date] => 2000-09-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/664848 | Globally distributed scan blocks | Sep 18, 2000 | Issued |
Array
(
[id] => 984761
[patent_doc_number] => 06928593
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[patent_issue_date] => 2005-08-09
[patent_title] => 'Memory module and memory component built-in self test'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/664910 | Memory module and memory component built-in self test | Sep 17, 2000 | Issued |
Array
(
[id] => 1110004
[patent_doc_number] => 06813743
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[patent_title] => 'Sliding window technique for map decoders'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/629122 | Sliding window technique for map decoders | Jul 30, 2000 | Issued |
Array
(
[id] => 1192672
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[patent_title] => 'Unidirectional verification of bus-based systems'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/626290 | Unidirectional verification of bus-based systems | Jul 24, 2000 | Issued |
Array
(
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[patent_title] => 'Coding sublayer for multi-channel media with error correction'
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Array
(
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Array
(
[id] => 1234553
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Array
(
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[patent_title] => 'Method of analyzing a relief of failure cell in a memory and memory testing apparatus having a failure relief analyzer using the method'
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Array
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Array
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