Elly Gerald Stoica
Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )
Most Active Art Unit | 1647 |
Art Unit(s) | 1647, 1646 |
Total Applications | 1381 |
Issued Applications | 805 |
Pending Applications | 99 |
Abandoned Applications | 477 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 16292162
[patent_doc_number] => 10769013
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-09-08
[patent_title] => Caching error checking data for memory having inline storage configurations
[patent_app_type] => utility
[patent_app_number] => 16/005427
[patent_app_country] => US
[patent_app_date] => 2018-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 21888
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16005427
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/005427 | Caching error checking data for memory having inline storage configurations | Jun 10, 2018 | Issued |
Array
(
[id] => 15235665
[patent_doc_number] => 10505566
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-10
[patent_title] => Methods and apparatus for encoding and decoding based on layered polar code
[patent_app_type] => utility
[patent_app_number] => 16/004859
[patent_app_country] => US
[patent_app_date] => 2018-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 19862
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004859
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/004859 | Methods and apparatus for encoding and decoding based on layered polar code | Jun 10, 2018 | Issued |
Array
(
[id] => 16385239
[patent_doc_number] => 10810077
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-10-20
[patent_title] => Rapid soft-error detection
[patent_app_type] => utility
[patent_app_number] => 16/004645
[patent_app_country] => US
[patent_app_date] => 2018-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 9228
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004645
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/004645 | Rapid soft-error detection | Jun 10, 2018 | Issued |
Array
(
[id] => 14137559
[patent_doc_number] => 20190103169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-04
[patent_title] => MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/970298
[patent_app_country] => US
[patent_app_date] => 2018-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6306
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15970298
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/970298 | Memory system and method of operating the same | May 2, 2018 | Issued |
Array
(
[id] => 15042939
[patent_doc_number] => 20190332474
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-31
[patent_title] => SCALE OUT DATA PROTECTION WITH ERASURE CODING
[patent_app_type] => utility
[patent_app_number] => 15/965453
[patent_app_country] => US
[patent_app_date] => 2018-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9211
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15965453
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/965453 | Scale out data protection with erasure coding | Apr 26, 2018 | Issued |
Array
(
[id] => 16186055
[patent_doc_number] => 10719387
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-21
[patent_title] => Memory interface with tamper-evident features to enhance software security
[patent_app_type] => utility
[patent_app_number] => 15/962783
[patent_app_country] => US
[patent_app_date] => 2018-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 7814
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962783
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/962783 | Memory interface with tamper-evident features to enhance software security | Apr 24, 2018 | Issued |
Array
(
[id] => 15951229
[patent_doc_number] => 10663514
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-26
[patent_title] => Virtual probe sequencing
[patent_app_type] => utility
[patent_app_number] => 15/959895
[patent_app_country] => US
[patent_app_date] => 2018-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 3746
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959895
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/959895 | Virtual probe sequencing | Apr 22, 2018 | Issued |
Array
(
[id] => 16462827
[patent_doc_number] => 10846175
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-24
[patent_title] => High throughput bit correction of data inside a word buffer for a product code decoder
[patent_app_type] => utility
[patent_app_number] => 15/950137
[patent_app_country] => US
[patent_app_date] => 2018-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 13124
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950137
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/950137 | High throughput bit correction of data inside a word buffer for a product code decoder | Apr 9, 2018 | Issued |
Array
(
[id] => 18136231
[patent_doc_number] => 11561910
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-24
[patent_title] => In-band retimer register access
[patent_app_type] => utility
[patent_app_number] => 15/942160
[patent_app_country] => US
[patent_app_date] => 2018-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 13983
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942160
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/942160 | In-band retimer register access | Mar 29, 2018 | Issued |
Array
(
[id] => 17530682
[patent_doc_number] => 11303392
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-12
[patent_title] => Multi-HARQ methods and apparatus for codeblock group based transmissions
[patent_app_type] => utility
[patent_app_number] => 15/919157
[patent_app_country] => US
[patent_app_date] => 2018-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 19295
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919157
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/919157 | Multi-HARQ methods and apparatus for codeblock group based transmissions | Mar 11, 2018 | Issued |
Array
(
[id] => 12825979
[patent_doc_number] => 20180167165
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-14
[patent_title] => ITERATIVE MULTI-LEVEL EQUALIZATION AND DECODING
[patent_app_type] => utility
[patent_app_number] => 15/889867
[patent_app_country] => US
[patent_app_date] => 2018-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3626
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889867
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/889867 | Iterative multi-level equalization and decoding | Feb 5, 2018 | Issued |
Array
(
[id] => 13782713
[patent_doc_number] => 20190004895
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-03
[patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/879512
[patent_app_country] => US
[patent_app_date] => 2018-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13528
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879512
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/879512 | Memory system and operating method thereof | Jan 24, 2018 | Issued |
Array
(
[id] => 16803960
[patent_doc_number] => 10998922
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-04
[patent_title] => Turbo product polar coding with hard decision cleaning
[patent_app_type] => utility
[patent_app_number] => 15/866594
[patent_app_country] => US
[patent_app_date] => 2018-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 31
[patent_no_of_words] => 23748
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866594
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/866594 | Turbo product polar coding with hard decision cleaning | Jan 9, 2018 | Issued |
Array
(
[id] => 18402671
[patent_doc_number] => 11664824
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-30
[patent_title] => Systems and methods for fast layered decoding for low-density parity-check (LDPC) codes
[patent_app_type] => utility
[patent_app_number] => 16/476599
[patent_app_country] => US
[patent_app_date] => 2018-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8769
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476599
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/476599 | Systems and methods for fast layered decoding for low-density parity-check (LDPC) codes | Jan 8, 2018 | Issued |
Array
(
[id] => 18074283
[patent_doc_number] => 11533128
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => Rate-matching scheme for control channels using polar codes
[patent_app_type] => utility
[patent_app_number] => 16/468622
[patent_app_country] => US
[patent_app_date] => 2018-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 12019
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16468622
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/468622 | Rate-matching scheme for control channels using polar codes | Jan 7, 2018 | Issued |
Array
(
[id] => 12852145
[patent_doc_number] => 20180175888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => EFFICIENT ENCODING/DECODING FOR MULTIPLE-INPUT MULTIPLE-OUTPUT OPERATING WITH TWO CODEWORDS
[patent_app_type] => utility
[patent_app_number] => 15/837112
[patent_app_country] => US
[patent_app_date] => 2017-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3811
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837112
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/837112 | EFFICIENT ENCODING/DECODING FOR MULTIPLE-INPUT MULTIPLE-OUTPUT OPERATING WITH TWO CODEWORDS | Dec 10, 2017 | Abandoned |
Array
(
[id] => 16172619
[patent_doc_number] => 10714195
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-14
[patent_title] => Read disturb detection and recovery with adaptive thresholding for 3-D NAND storage
[patent_app_type] => utility
[patent_app_number] => 15/835246
[patent_app_country] => US
[patent_app_date] => 2017-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8424
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835246
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/835246 | Read disturb detection and recovery with adaptive thresholding for 3-D NAND storage | Dec 6, 2017 | Issued |
Array
(
[id] => 15757845
[patent_doc_number] => 10621035
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-14
[patent_title] => Techniques for correcting data errors in memory devices
[patent_app_type] => utility
[patent_app_number] => 15/787644
[patent_app_country] => US
[patent_app_date] => 2017-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 8836
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15787644
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/787644 | Techniques for correcting data errors in memory devices | Oct 17, 2017 | Issued |
Array
(
[id] => 14137557
[patent_doc_number] => 20190103168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-04
[patent_title] => ERROR REDUCING MATRIX GENERATION
[patent_app_type] => utility
[patent_app_number] => 15/725255
[patent_app_country] => US
[patent_app_date] => 2017-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8807
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725255
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/725255 | Error reducing matrix generation | Oct 3, 2017 | Issued |
Array
(
[id] => 14448017
[patent_doc_number] => 20190181882
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => DETERMINING ELEMENTS OF BASE MATRICES FOR QUASI-CYCLIC LDPC CODES HAVING VARIABLE CODE LENGTHS
[patent_app_type] => utility
[patent_app_number] => 16/324995
[patent_app_country] => US
[patent_app_date] => 2017-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5905
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16324995
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/324995 | DETERMINING ELEMENTS OF BASE MATRICES FOR QUASI-CYCLIC LDPC CODES HAVING VARIABLE CODE LENGTHS | Aug 8, 2017 | Abandoned |