Search

Elly Gerald Stoica

Examiner (ID: 13856, Phone: (571)272-9941 , Office: P/1647 )

Most Active Art Unit
1647
Art Unit(s)
1647, 1646
Total Applications
1381
Issued Applications
805
Pending Applications
99
Abandoned Applications
477

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14614811 [patent_doc_number] => 10360106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Throttled real-time writes [patent_app_type] => utility [patent_app_number] => 15/409386 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 11386 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409386 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/409386
Throttled real-time writes Jan 17, 2017 Issued
Array ( [id] => 12474987 [patent_doc_number] => 09990247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Write mapping to mitigate hard errors via soft-decision decoding [patent_app_type] => utility [patent_app_number] => 15/407444 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15407444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/407444
Write mapping to mitigate hard errors via soft-decision decoding Jan 16, 2017 Issued
Array ( [id] => 11608947 [patent_doc_number] => 20170126252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME' [patent_app_type] => utility [patent_app_number] => 15/403394 [patent_app_country] => US [patent_app_date] => 2017-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6938 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/403394
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same Jan 10, 2017 Issued
Array ( [id] => 14669235 [patent_doc_number] => 10372519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management [patent_app_type] => utility [patent_app_number] => 15/374662 [patent_app_country] => US [patent_app_date] => 2016-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15374662 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/374662
Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management Dec 8, 2016 Issued
Array ( [id] => 13708801 [patent_doc_number] => 20170365355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => MEMORY CONTROLLER FOR SELECTING READ CLOCK SIGNAL [patent_app_type] => utility [patent_app_number] => 15/364274 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364274
Memory controller for selecting read clock signal Nov 29, 2016 Issued
Array ( [id] => 15640837 [patent_doc_number] => 10593421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Method and apparatus for logically removing defective pages in non-volatile memory storage device [patent_app_type] => utility [patent_app_number] => 15/365800 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6969 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365800 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365800
Method and apparatus for logically removing defective pages in non-volatile memory storage device Nov 29, 2016 Issued
Array ( [id] => 12220818 [patent_doc_number] => 20180059178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'INTEGRATED CIRCUIT WITH LOW POWER SCAN SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/365890 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5670 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365890 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365890
Integrated circuit with low power scan system Nov 29, 2016 Issued
Array ( [id] => 15582123 [patent_doc_number] => 10581462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Signature-enabled polar encoder and decoder [patent_app_type] => utility [patent_app_number] => 15/364521 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6397 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364521 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364521
Signature-enabled polar encoder and decoder Nov 29, 2016 Issued
Array ( [id] => 12241261 [patent_doc_number] => 20180074124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'IMPORTANCE SAMPLING METHOD FOR MULTIPLE FAILURE REGIONS' [patent_app_type] => utility [patent_app_number] => 15/365808 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365808 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365808
Importance sampling method for multiple failure regions Nov 29, 2016 Issued
Array ( [id] => 11503765 [patent_doc_number] => 20170077950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'Matrix-Based Error Correction and Erasure Code Methods and System and Applications Thereof' [patent_app_type] => utility [patent_app_number] => 15/362360 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 31394 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362360 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/362360
Matrix-based error correction and erasure code methods and system and applications thereof Nov 27, 2016 Issued
Array ( [id] => 14982191 [patent_doc_number] => 10445006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Adjusting a dispersal parameter of dispersedly stored data [patent_app_type] => utility [patent_app_number] => 15/350762 [patent_app_country] => US [patent_app_date] => 2016-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 19139 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15350762 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/350762
Adjusting a dispersal parameter of dispersedly stored data Nov 13, 2016 Issued
Array ( [id] => 16654202 [patent_doc_number] => 10931400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Decoding method and apparatus in wireless communication system [patent_app_type] => utility [patent_app_number] => 15/774963 [patent_app_country] => US [patent_app_date] => 2016-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9626 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15774963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/774963
Decoding method and apparatus in wireless communication system Nov 8, 2016 Issued
Array ( [id] => 13176071 [patent_doc_number] => 10104168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Method for managing throughput in a distributed storage network [patent_app_type] => utility [patent_app_number] => 15/281430 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6890 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/281430
Method for managing throughput in a distributed storage network Sep 29, 2016 Issued
Array ( [id] => 11398715 [patent_doc_number] => 20170019253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'DECRYPTING SEGMENTED DATA IN A DISTRIBUTED COMPUTING SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/281317 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12162 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281317 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/281317
DECRYPTING SEGMENTED DATA IN A DISTRIBUTED COMPUTING SYSTEM Sep 29, 2016 Abandoned
Array ( [id] => 11386588 [patent_doc_number] => 20170012644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/272189 [patent_app_country] => US [patent_app_date] => 2016-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5726 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272189 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272189
Low density parity check encoder having length of 16200 and code rate of 2/15, and low density parity check encoding method using the same Sep 20, 2016 Issued
Array ( [id] => 15198103 [patent_doc_number] => 10496546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Cache memory and processor system [patent_app_type] => utility [patent_app_number] => 15/257163 [patent_app_country] => US [patent_app_date] => 2016-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4325 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15257163 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/257163
Cache memory and processor system Sep 5, 2016 Issued
Array ( [id] => 11352674 [patent_doc_number] => 20160371414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'CIRCUIT DESIGN SUPPORT METHOD, CIRCUIT DESIGN SUPPORT APPARATUS, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 15/254375 [patent_app_country] => US [patent_app_date] => 2016-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 15507 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15254375 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/254375
CIRCUIT DESIGN SUPPORT METHOD, CIRCUIT DESIGN SUPPORT APPARATUS, AND RECORDING MEDIUM Aug 31, 2016 Abandoned
Array ( [id] => 11556746 [patent_doc_number] => 20170102992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'Memory Module with Integrated Error Correction' [patent_app_type] => utility [patent_app_number] => 15/254431 [patent_app_country] => US [patent_app_date] => 2016-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3682 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15254431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/254431
Memory module with integrated error correction Aug 31, 2016 Issued
Array ( [id] => 11354472 [patent_doc_number] => 20160373214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'DATA TRANSMISSION METHOD AND COMMUNICATIONS DEVICE' [patent_app_type] => utility [patent_app_number] => 15/248790 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15248790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/248790
Data transmission method and communications device Aug 25, 2016 Issued
Array ( [id] => 11984661 [patent_doc_number] => 20170288816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'METHOD AND SYSTEM FOR COMPENSATING HLS SLICE LOSS' [patent_app_type] => utility [patent_app_number] => 15/246243 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4767 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15246243 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/246243
METHOD AND SYSTEM FOR COMPENSATING HLS SLICE LOSS Aug 23, 2016 Abandoned
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