Search

Elvis O. Price

Examiner (ID: 16750, Phone: (571)272-0644 , Office: P/1671 )

Most Active Art Unit
1621
Art Unit(s)
1621, 1671
Total Applications
1230
Issued Applications
1010
Pending Applications
52
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17949272 [patent_doc_number] => 20220336291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => NOVEL GATE STRUCTURES FOR TUNING THRESHOLD VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/810799 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11985 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810799
Gate structures for tuning threshold voltage Jul 4, 2022 Issued
Array ( [id] => 19183875 [patent_doc_number] => 11990476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Semiconductor nanowire device having (111)-plane channel sidewalls [patent_app_type] => utility [patent_app_number] => 17/842450 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 10820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842450
Semiconductor nanowire device having (111)-plane channel sidewalls Jun 15, 2022 Issued
Array ( [id] => 19341499 [patent_doc_number] => 12051696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Method of fabricating a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/840060 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7493 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840060 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/840060
Method of fabricating a semiconductor device Jun 13, 2022 Issued
Array ( [id] => 17886471 [patent_doc_number] => 20220301949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => METHOD OF MEASURING CONCENTRATION OF FE IN P-TYPE SILICON WAFER AND SPV MEASUREMENT APPARATUS [patent_app_type] => utility [patent_app_number] => 17/834412 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834412
Method of measuring concentration of Fe in p-type silicon wafer and SPV measurement apparatus Jun 6, 2022 Issued
Array ( [id] => 18812603 [patent_doc_number] => 20230386940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/824263 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824263
Method for forming semiconductor structure May 24, 2022 Issued
Array ( [id] => 18789420 [patent_doc_number] => 20230378082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => OVERLAY MARK [patent_app_type] => utility [patent_app_number] => 17/749140 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749140
Overlay mark May 19, 2022 Issued
Array ( [id] => 17855118 [patent_doc_number] => 20220285161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => Methods for Doping High-K Metal Gates for Tuning Threshold Voltages [patent_app_type] => utility [patent_app_number] => 17/664325 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664325
Methods for doping high-K metal gates for tuning threshold voltages May 19, 2022 Issued
Array ( [id] => 17840693 [patent_doc_number] => 20220277999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A POLYMER SUPPORT LAYER [patent_app_type] => utility [patent_app_number] => 17/663863 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663863 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663863
Process of forming an electronic device including a polymer support layer May 17, 2022 Issued
Array ( [id] => 19168445 [patent_doc_number] => 11984358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Systems and methods for improving within die co-planarity uniformity [patent_app_type] => utility [patent_app_number] => 17/742962 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 7232 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742962 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742962
Systems and methods for improving within die co-planarity uniformity May 11, 2022 Issued
Array ( [id] => 18068272 [patent_doc_number] => 20220399360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/721533 [patent_app_country] => US [patent_app_date] => 2022-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721533
Semiconductor device and data storage system including the same Apr 14, 2022 Issued
Array ( [id] => 19679338 [patent_doc_number] => 12191210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Formation of high density 3D circuits with enhanced 3D conductivity [patent_app_type] => utility [patent_app_number] => 17/721124 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 12924 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721124
Formation of high density 3D circuits with enhanced 3D conductivity Apr 13, 2022 Issued
Array ( [id] => 17963628 [patent_doc_number] => 20220344209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => HIGH DENSITY 3D ROUTING WITH ROTATIONAL SYMMETRY FOR A PLURALITY OF 3D DEVICES [patent_app_type] => utility [patent_app_number] => 17/718196 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718196
HIGH DENSITY 3D ROUTING WITH ROTATIONAL SYMMETRY FOR A PLURALITY OF 3D DEVICES Apr 10, 2022 Pending
Array ( [id] => 17949696 [patent_doc_number] => 20220336715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => METHOD OF MANUFACTURING LED DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/658743 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/658743
Method of manufacturing LED display panel Apr 10, 2022 Issued
Array ( [id] => 19430011 [patent_doc_number] => 12089465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/713549 [patent_app_country] => US [patent_app_date] => 2022-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 37 [patent_no_of_words] => 20607 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713549 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/713549
Display device Apr 4, 2022 Issued
Array ( [id] => 19926354 [patent_doc_number] => 12300649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/702259 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 2335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/702259
Semiconductor package Mar 22, 2022 Issued
Array ( [id] => 17871052 [patent_doc_number] => 20220293789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => 3D DEVICE WITH A PLURALITY OF CORE WIRING LAYOUT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/691840 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/691840
3D device with a plurality of core wiring layout architecture Mar 9, 2022 Issued
Array ( [id] => 17855403 [patent_doc_number] => 20220285446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/687451 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/687451
Display panel and electronic device including the same Mar 3, 2022 Issued
Array ( [id] => 18983671 [patent_doc_number] => 11908860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Integrated chip with improved latch-up immunity [patent_app_type] => utility [patent_app_number] => 17/673030 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 58 [patent_no_of_words] => 20022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673030
Integrated chip with improved latch-up immunity Feb 15, 2022 Issued
Array ( [id] => 19973969 [patent_doc_number] => 12342603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Plurality of devices in adjacent 3D stacks in different circuit locations [patent_app_type] => utility [patent_app_number] => 17/592032 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 2511 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/592032
Plurality of devices in adjacent 3D stacks in different circuit locations Feb 2, 2022 Issued
Array ( [id] => 17780302 [patent_doc_number] => 20220246652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => PHOTOELECTRIC CONVERSION DEVICE AND PHOTOELECTRIC CONVERSION SYSTEM [patent_app_type] => utility [patent_app_number] => 17/588039 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588039
Photoelectric conversion device and photoelectric conversion system Jan 27, 2022 Issued
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