
Eman A. Alkafawi
Examiner (ID: 10826, Phone: (571)272-4448 , Office: P/2865 )
| Most Active Art Unit | 2865 |
| Art Unit(s) | 2864, 2858, 2865, 2857 |
| Total Applications | 335 |
| Issued Applications | 192 |
| Pending Applications | 4 |
| Abandoned Applications | 140 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11725393
[patent_doc_number] => 09698260
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-07-04
[patent_title] => 'High voltage device with low Rdson'
[patent_app_type] => utility
[patent_app_number] => 14/985455
[patent_app_country] => US
[patent_app_date] => 2015-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 10507
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14985455
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/985455 | High voltage device with low Rdson | Dec 30, 2015 | Issued |
Array
(
[id] => 10826245
[patent_doc_number] => 20160172412
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-16
[patent_title] => 'IMAGE SENSORS INCLUDING NON-ALIGNED GRID PATTERNS'
[patent_app_type] => utility
[patent_app_number] => 14/970889
[patent_app_country] => US
[patent_app_date] => 2015-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10191
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14970889
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/970889 | Image sensors including non-aligned grid patterns | Dec 15, 2015 | Issued |
Array
(
[id] => 11694346
[patent_doc_number] => 20170170063
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-15
[patent_title] => 'MODULATING MICROSTRUCTURE IN INTERCONNECTS'
[patent_app_type] => utility
[patent_app_number] => 14/965991
[patent_app_country] => US
[patent_app_date] => 2015-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3039
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965991
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/965991 | Modulating microstructure in interconnects | Dec 10, 2015 | Issued |
Array
(
[id] => 11321674
[patent_doc_number] => 09520423
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-12-13
[patent_title] => 'Image sensors including non-aligned grid patterns'
[patent_app_type] => utility
[patent_app_number] => 14/966587
[patent_app_country] => US
[patent_app_date] => 2015-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 10178
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14966587
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/966587 | Image sensors including non-aligned grid patterns | Dec 10, 2015 | Issued |
Array
(
[id] => 13695109
[patent_doc_number] => 20170358509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-14
[patent_title] => PROCESS OF ENCAPSULATING ELECTRONIC COMPONENTS
[patent_app_type] => utility
[patent_app_number] => 15/531811
[patent_app_country] => US
[patent_app_date] => 2015-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2196
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15531811
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/531811 | Process of encapsulating electronic components | Nov 30, 2015 | Issued |
Array
(
[id] => 11666071
[patent_doc_number] => 20170154790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-01
[patent_title] => 'SAM ASSISTED SELECTIVE E-LESS PLATING ON PACKAGING MATERIALS'
[patent_app_type] => utility
[patent_app_number] => 14/954359
[patent_app_country] => US
[patent_app_date] => 2015-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3100
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954359
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/954359 | SAM ASSISTED SELECTIVE E-LESS PLATING ON PACKAGING MATERIALS | Nov 29, 2015 | Abandoned |
Array
(
[id] => 13257189
[patent_doc_number] => 10141291
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-27
[patent_title] => Semiconductor device and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 14/954416
[patent_app_country] => US
[patent_app_date] => 2015-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 5159
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954416
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/954416 | Semiconductor device and method of manufacturing the same | Nov 29, 2015 | Issued |
Array
(
[id] => 12293892
[patent_doc_number] => 09934985
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-03
[patent_title] => Critical dimension control for double patterning process
[patent_app_type] => utility
[patent_app_number] => 14/954380
[patent_app_country] => US
[patent_app_date] => 2015-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 23
[patent_no_of_words] => 11644
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954380
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/954380 | Critical dimension control for double patterning process | Nov 29, 2015 | Issued |
Array
(
[id] => 11889383
[patent_doc_number] => 09759941
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-12
[patent_title] => 'Array substrate used in liquid crystal panel and manufacturing method for the same'
[patent_app_type] => utility
[patent_app_number] => 14/901250
[patent_app_country] => US
[patent_app_date] => 2015-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3510
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14901250
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/901250 | Array substrate used in liquid crystal panel and manufacturing method for the same | Nov 26, 2015 | Issued |
Array
(
[id] => 15428087
[patent_doc_number] => 10546983
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-28
[patent_title] => Lighting device having a 3D scattering element and optical extractor with convex output surface
[patent_app_type] => utility
[patent_app_number] => 15/529458
[patent_app_country] => US
[patent_app_date] => 2015-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 8942
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15529458
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/529458 | Lighting device having a 3D scattering element and optical extractor with convex output surface | Nov 24, 2015 | Issued |
Array
(
[id] => 10719060
[patent_doc_number] => 20160065207
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-03
[patent_title] => 'HIGH VOLTAGE CONTROL CIRCUIT FOR AN ELECTRONIC SWITCH'
[patent_app_type] => utility
[patent_app_number] => 14/935859
[patent_app_country] => US
[patent_app_date] => 2015-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 14133
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935859
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/935859 | HIGH VOLTAGE CONTROL CIRCUIT FOR AN ELECTRONIC SWITCH | Nov 8, 2015 | Abandoned |
Array
(
[id] => 11346462
[patent_doc_number] => 09530878
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-12-27
[patent_title] => 'III-N material structure for gate-recessed transistors'
[patent_app_type] => utility
[patent_app_number] => 14/935346
[patent_app_country] => US
[patent_app_date] => 2015-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 7579
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935346
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/935346 | III-N material structure for gate-recessed transistors | Nov 5, 2015 | Issued |
Array
(
[id] => 10780083
[patent_doc_number] => 20160126239
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-05
[patent_title] => 'INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM MIM CAPACITOR MATERIAL AND METHODS FOR FABRICATING SAME'
[patent_app_type] => utility
[patent_app_number] => 14/928272
[patent_app_country] => US
[patent_app_date] => 2015-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3907
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14928272
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/928272 | Integrated circuits with resistor structures formed from MIM capacitor material and methods for fabricating same | Oct 29, 2015 | Issued |
Array
(
[id] => 10984464
[patent_doc_number] => 20160181409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'Bidirectional Power Switching with Bipolar Conduction and with Two Control Terminals Gated by Two Merged Transistors'
[patent_app_type] => utility
[patent_app_number] => 14/918440
[patent_app_country] => US
[patent_app_date] => 2015-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7048
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918440
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/918440 | Bidirectional Power Switching with Bipolar Conduction and with Two Control Terminals Gated by Two Merged Transistors | Oct 19, 2015 | Abandoned |
Array
(
[id] => 11571847
[patent_doc_number] => 20170110491
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-20
[patent_title] => 'SEMICONDUCTOR ON INSULATOR SUBSTRATE WITH BACK BIAS'
[patent_app_type] => utility
[patent_app_number] => 14/918537
[patent_app_country] => US
[patent_app_date] => 2015-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6601
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918537
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/918537 | Semiconductor on insulator substrate with back bias | Oct 19, 2015 | Issued |
Array
(
[id] => 10809775
[patent_doc_number] => 20160155934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-02
[patent_title] => 'MAGNETIC RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/887506
[patent_app_country] => US
[patent_app_date] => 2015-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 11412
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14887506
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/887506 | Magnetic random access memory devices and methods of manufacturing the same | Oct 19, 2015 | Issued |
Array
(
[id] => 10674103
[patent_doc_number] => 20160020248
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-21
[patent_title] => 'ACTIVE LED MODULE WITH LED AND TRANSISTOR FORMED ON SAME SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 14/868082
[patent_app_country] => US
[patent_app_date] => 2015-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7295
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868082
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/868082 | Active LED module with LED and transistor formed on same substrate | Sep 27, 2015 | Issued |
Array
(
[id] => 10741023
[patent_doc_number] => 20160087173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-24
[patent_title] => 'SELF-ALIGNED FLOATING MIRROR FOR CONTACT VIAS'
[patent_app_type] => utility
[patent_app_number] => 14/860483
[patent_app_country] => US
[patent_app_date] => 2015-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 22141
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14860483
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/860483 | Self-aligned floating mirror for contact vias | Sep 20, 2015 | Issued |
Array
(
[id] => 10741023
[patent_doc_number] => 20160087173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-24
[patent_title] => 'SELF-ALIGNED FLOATING MIRROR FOR CONTACT VIAS'
[patent_app_type] => utility
[patent_app_number] => 14/860483
[patent_app_country] => US
[patent_app_date] => 2015-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 22141
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14860483
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/860483 | Self-aligned floating mirror for contact vias | Sep 20, 2015 | Issued |
Array
(
[id] => 14460071
[patent_doc_number] => 10326010
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-06-18
[patent_title] => Semiconductor device and method of manufacturing the semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/311524
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10405
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 371
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15311524
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/311524 | Semiconductor device and method of manufacturing the semiconductor device | Sep 17, 2015 | Issued |