![](/images/general/no_picture/200_user.png)
Emmanuel Bayard
Examiner (ID: 15217, Phone: (571)272-3016 , Office: P/2633 )
Most Active Art Unit | 2633 |
Art Unit(s) | 2611, 2638, 2731, 2631, 2633 |
Total Applications | 1976 |
Issued Applications | 1675 |
Pending Applications | 147 |
Abandoned Applications | 153 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3561998
[patent_doc_number] => 05572547
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'System for controlling the operating mode of an adaptive equalizer'
[patent_app_type] => 1
[patent_app_number] => 8/539149
[patent_app_country] => US
[patent_app_date] => 1995-10-04
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[patent_no_of_words] => 3254
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[pdf_file] => patents/05/572/05572547.pdf
[firstpage_image] =>[orig_patent_app_number] => 539149
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/539149 | System for controlling the operating mode of an adaptive equalizer | Oct 3, 1995 | Issued |
Array
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[patent_doc_number] => 05550874
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Clock synchronizing circuit of data transmission system'
[patent_app_type] => 1
[patent_app_number] => 8/519436
[patent_app_country] => US
[patent_app_date] => 1995-08-25
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[firstpage_image] =>[orig_patent_app_number] => 519436
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/519436 | Clock synchronizing circuit of data transmission system | Aug 24, 1995 | Issued |
Array
(
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[patent_doc_number] => 05535249
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[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Precise detection of frequency error for bursts modulated by predetermined symbol sequence'
[patent_app_type] => 1
[patent_app_number] => 8/498750
[patent_app_country] => US
[patent_app_date] => 1995-07-06
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[patent_no_of_words] => 3821
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[firstpage_image] =>[orig_patent_app_number] => 498750
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/498750 | Precise detection of frequency error for bursts modulated by predetermined symbol sequence | Jul 5, 1995 | Issued |
Array
(
[id] => 3613996
[patent_doc_number] => 05579337
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'System employing dissipative pseudorandom dynamics and selective feedback for communications and measurement'
[patent_app_type] => 1
[patent_app_number] => 8/491624
[patent_app_country] => US
[patent_app_date] => 1995-06-19
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[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 5264
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/491624 | System employing dissipative pseudorandom dynamics and selective feedback for communications and measurement | Jun 18, 1995 | Issued |
Array
(
[id] => 3624074
[patent_doc_number] => 05566214
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Automatic noise normalization and reacquisition control for a QPSK demodulator symbol tracking loop'
[patent_app_type] => 1
[patent_app_number] => 8/491667
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/491667 | Automatic noise normalization and reacquisition control for a QPSK demodulator symbol tracking loop | Jun 18, 1995 | Issued |
Array
(
[id] => 3847163
[patent_doc_number] => 05815540
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-29
[patent_title] => 'Semiconductor integrated circuit device including PLL circuit'
[patent_app_type] => 1
[patent_app_number] => 8/466459
[patent_app_country] => US
[patent_app_date] => 1995-06-06
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[firstpage_image] =>[orig_patent_app_number] => 466459
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/466459 | Semiconductor integrated circuit device including PLL circuit | Jun 5, 1995 | Issued |
Array
(
[id] => 3545909
[patent_doc_number] => 05557646
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-17
[patent_title] => 'Multipath eliminating filter'
[patent_app_type] => 1
[patent_app_number] => 8/451502
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[patent_app_date] => 1995-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_no_of_words] => 9904
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[pdf_file] => patents/05/557/05557646.pdf
[firstpage_image] =>[orig_patent_app_number] => 451502
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/451502 | Multipath eliminating filter | May 25, 1995 | Issued |
Array
(
[id] => 3528165
[patent_doc_number] => 05577078
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Edge detector'
[patent_app_type] => 1
[patent_app_number] => 8/452446
[patent_app_country] => US
[patent_app_date] => 1995-05-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/577/05577078.pdf
[firstpage_image] =>[orig_patent_app_number] => 452446
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/452446 | Edge detector | May 25, 1995 | Issued |
Array
(
[id] => 3537757
[patent_doc_number] => 05528638
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Multiple phase shifted clocks generation using a minimal set of signals from a PLL'
[patent_app_type] => 1
[patent_app_number] => 8/449355
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[patent_app_date] => 1995-05-24
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[pdf_file] => patents/05/528/05528638.pdf
[firstpage_image] =>[orig_patent_app_number] => 449355
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/449355 | Multiple phase shifted clocks generation using a minimal set of signals from a PLL | May 23, 1995 | Issued |
Array
(
[id] => 3624046
[patent_doc_number] => 05566212
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Phase-locked loop circuit for Manchester-data decoding'
[patent_app_type] => 1
[patent_app_number] => 8/427013
[patent_app_country] => US
[patent_app_date] => 1995-04-24
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[pdf_file] => patents/05/566/05566212.pdf
[firstpage_image] =>[orig_patent_app_number] => 427013
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/427013 | Phase-locked loop circuit for Manchester-data decoding | Apr 23, 1995 | Issued |
Array
(
[id] => 3560554
[patent_doc_number] => 05548622
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Method and structure for synchronization of asynchronous signals'
[patent_app_type] => 1
[patent_app_number] => 8/409744
[patent_app_country] => US
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[pdf_file] => patents/05/548/05548622.pdf
[firstpage_image] =>[orig_patent_app_number] => 409744
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/409744 | Method and structure for synchronization of asynchronous signals | Mar 23, 1995 | Issued |
Array
(
[id] => 3560586
[patent_doc_number] => 05548624
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Destuff circuit for asynchronous digital signals'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 404286
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/404286 | Destuff circuit for asynchronous digital signals | Mar 13, 1995 | Issued |
Array
(
[id] => 3610008
[patent_doc_number] => 05559830
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[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Equalization system for AM compatible digital receiver'
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[patent_app_number] => 8/376986
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[pdf_file] => patents/05/559/05559830.pdf
[firstpage_image] =>[orig_patent_app_number] => 376986
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/376986 | Equalization system for AM compatible digital receiver | Jan 22, 1995 | Issued |
Array
(
[id] => 3560508
[patent_doc_number] => 05548619
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[patent_issue_date] => 1996-08-20
[patent_title] => 'Radio receiver apparatus of orthogonal detection type comprising local oscillator means with improved automatic frequency control arrangement'
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[pdf_file] => patents/05/548/05548619.pdf
[firstpage_image] =>[orig_patent_app_number] => 374915
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/374915 | Radio receiver apparatus of orthogonal detection type comprising local oscillator means with improved automatic frequency control arrangement | Jan 18, 1995 | Issued |
Array
(
[id] => 3528292
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[patent_issue_date] => 1996-11-19
[patent_title] => 'Clock signal generation circuit capable of operating at high speed with high frequency'
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[firstpage_image] =>[orig_patent_app_number] => 365479
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/365479 | Clock signal generation circuit capable of operating at high speed with high frequency | Dec 27, 1994 | Issued |
Array
(
[id] => 3573878
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[patent_kind] => NA
[patent_issue_date] => 1996-06-11
[patent_title] => 'Blind multipath correction for digital communication channel'
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[firstpage_image] =>[orig_patent_app_number] => 355944
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/355944 | Blind multipath correction for digital communication channel | Dec 13, 1994 | Issued |
Array
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[id] => 3567461
[patent_doc_number] => 05544200
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[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Acquisition of carrier phase and symbol timing through joint estimation of phase and timing adjustments'
[patent_app_type] => 1
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Array
(
[id] => 3501808
[patent_doc_number] => 05561690
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[patent_issue_date] => 1996-10-01
[patent_title] => 'High speed variable length code decoding apparatus'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/346067 | High speed variable length code decoding apparatus | Nov 28, 1994 | Issued |
Array
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Array
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[patent_issue_date] => 1996-04-09
[patent_title] => 'Methods and apparatus for estimating carrier-to-interference ratios at cellular radio base stations'
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[pdf_file] => patents/05/506/05506869.pdf
[firstpage_image] =>[orig_patent_app_number] => 329922
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/329922 | Methods and apparatus for estimating carrier-to-interference ratios at cellular radio base stations | Oct 26, 1994 | Issued |