Emmanuel Bayard
Examiner (ID: 15217, Phone: (571)272-3016 , Office: P/2633 )
Most Active Art Unit | 2633 |
Art Unit(s) | 2611, 2638, 2731, 2631, 2633 |
Total Applications | 1976 |
Issued Applications | 1675 |
Pending Applications | 147 |
Abandoned Applications | 153 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3593333
[patent_doc_number] => 05581585
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Phase-locked loop timing recovery circuit'
[patent_app_type] => 1
[patent_app_number] => 8/327184
[patent_app_country] => US
[patent_app_date] => 1994-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 3298
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/581/05581585.pdf
[firstpage_image] =>[orig_patent_app_number] => 327184
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/327184 | Phase-locked loop timing recovery circuit | Oct 20, 1994 | Issued |
Array
(
[id] => 3591240
[patent_doc_number] => 05499274
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-12
[patent_title] => 'Fractional bit-leaking clock signal resynchronizer for a high-speed digital communications system'
[patent_app_type] => 1
[patent_app_number] => 8/323031
[patent_app_country] => US
[patent_app_date] => 1994-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2751
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/499/05499274.pdf
[firstpage_image] =>[orig_patent_app_number] => 323031
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/323031 | Fractional bit-leaking clock signal resynchronizer for a high-speed digital communications system | Oct 13, 1994 | Issued |
Array
(
[id] => 3675081
[patent_doc_number] => 05598441
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Carrier acquisition technique for mobile radio QPSK demodulator'
[patent_app_type] => 1
[patent_app_number] => 8/322840
[patent_app_country] => US
[patent_app_date] => 1994-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 6209
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/598/05598441.pdf
[firstpage_image] =>[orig_patent_app_number] => 322840
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/322840 | Carrier acquisition technique for mobile radio QPSK demodulator | Oct 12, 1994 | Issued |
Array
(
[id] => 3547853
[patent_doc_number] => 05495512
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-27
[patent_title] => 'Hybrid phase locked loop'
[patent_app_type] => 1
[patent_app_number] => 8/314894
[patent_app_country] => US
[patent_app_date] => 1994-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2998
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/495/05495512.pdf
[firstpage_image] =>[orig_patent_app_number] => 314894
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/314894 | Hybrid phase locked loop | Sep 28, 1994 | Issued |
Array
(
[id] => 3468527
[patent_doc_number] => 05473641
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-05
[patent_title] => 'Frequency slaving apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/310310
[patent_app_country] => US
[patent_app_date] => 1994-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3149
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 358
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/473/05473641.pdf
[firstpage_image] =>[orig_patent_app_number] => 310310
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/310310 | Frequency slaving apparatus | Sep 21, 1994 | Issued |
Array
(
[id] => 3625185
[patent_doc_number] => 05511101
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-23
[patent_title] => 'Phase-locked loop synthesizer'
[patent_app_type] => 1
[patent_app_number] => 8/310843
[patent_app_country] => US
[patent_app_date] => 1994-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 3545
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/511/05511101.pdf
[firstpage_image] =>[orig_patent_app_number] => 310843
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/310843 | Phase-locked loop synthesizer | Sep 21, 1994 | Issued |
08/310230 | CIRCUIT FOR PREVENTING BASE LINE WANDER OF DIGITAL SIGNALS IN A NETWORK RECEIVER | Sep 20, 1994 | Abandoned |
Array
(
[id] => 3575415
[patent_doc_number] => 05483559
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-09
[patent_title] => 'Phase-locked loop device, oscillator, and signal processor'
[patent_app_type] => 1
[patent_app_number] => 8/309984
[patent_app_country] => US
[patent_app_date] => 1994-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 30
[patent_no_of_words] => 8805
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/483/05483559.pdf
[firstpage_image] =>[orig_patent_app_number] => 309984
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/309984 | Phase-locked loop device, oscillator, and signal processor | Sep 19, 1994 | Issued |
Array
(
[id] => 3531539
[patent_doc_number] => 05490179
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-06
[patent_title] => 'Signal grading in a selective call receiver for automatic gain control'
[patent_app_type] => 1
[patent_app_number] => 8/301087
[patent_app_country] => US
[patent_app_date] => 1994-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2138
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/490/05490179.pdf
[firstpage_image] =>[orig_patent_app_number] => 301087
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/301087 | Signal grading in a selective call receiver for automatic gain control | Sep 5, 1994 | Issued |
Array
(
[id] => 3429753
[patent_doc_number] => 05479452
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Method and apparatus for aligning a digital receiver'
[patent_app_type] => 1
[patent_app_number] => 8/300892
[patent_app_country] => US
[patent_app_date] => 1994-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8537
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479452.pdf
[firstpage_image] =>[orig_patent_app_number] => 300892
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/300892 | Method and apparatus for aligning a digital receiver | Sep 5, 1994 | Issued |
Array
(
[id] => 3524656
[patent_doc_number] => 05513225
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Resistorless phase locked loop circuit employing direct current injection'
[patent_app_type] => 1
[patent_app_number] => 8/298632
[patent_app_country] => US
[patent_app_date] => 1994-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 9667
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/513/05513225.pdf
[firstpage_image] =>[orig_patent_app_number] => 298632
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/298632 | Resistorless phase locked loop circuit employing direct current injection | Aug 30, 1994 | Issued |
Array
(
[id] => 3597696
[patent_doc_number] => 05553096
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Gain control using PWM'
[patent_app_type] => 1
[patent_app_number] => 8/298256
[patent_app_country] => US
[patent_app_date] => 1994-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2235
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/553/05553096.pdf
[firstpage_image] =>[orig_patent_app_number] => 298256
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/298256 | Gain control using PWM | Aug 29, 1994 | Issued |
08/298055 | SPREAD SPECTRUM COMMUNICATION APPARATUS | Aug 29, 1994 | Abandoned |
Array
(
[id] => 3538471
[patent_doc_number] => 05541956
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Adaptive equalizer and adaptive diversity equalizer'
[patent_app_type] => 1
[patent_app_number] => 8/292612
[patent_app_country] => US
[patent_app_date] => 1994-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 27
[patent_no_of_words] => 30638
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541956.pdf
[firstpage_image] =>[orig_patent_app_number] => 292612
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/292612 | Adaptive equalizer and adaptive diversity equalizer | Aug 17, 1994 | Issued |
Array
(
[id] => 3575401
[patent_doc_number] => 05483558
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-09
[patent_title] => 'Method and apparatus for detecting phase or frequency lock'
[patent_app_type] => 1
[patent_app_number] => 8/287562
[patent_app_country] => US
[patent_app_date] => 1994-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3185
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/483/05483558.pdf
[firstpage_image] =>[orig_patent_app_number] => 287562
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/287562 | Method and apparatus for detecting phase or frequency lock | Aug 7, 1994 | Issued |
Array
(
[id] => 3577902
[patent_doc_number] => 05485489
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-16
[patent_title] => 'Carrier recovery circuit for offset QPSK demodulators'
[patent_app_type] => 1
[patent_app_number] => 8/286464
[patent_app_country] => US
[patent_app_date] => 1994-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 24
[patent_no_of_words] => 6495
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 323
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/485/05485489.pdf
[firstpage_image] =>[orig_patent_app_number] => 286464
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/286464 | Carrier recovery circuit for offset QPSK demodulators | Aug 4, 1994 | Issued |
Array
(
[id] => 3593318
[patent_doc_number] => 05581584
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'PLL circuit'
[patent_app_type] => 1
[patent_app_number] => 8/277951
[patent_app_country] => US
[patent_app_date] => 1994-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1856
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/581/05581584.pdf
[firstpage_image] =>[orig_patent_app_number] => 277951
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/277951 | PLL circuit | Jul 19, 1994 | Issued |
Array
(
[id] => 3473114
[patent_doc_number] => 05469478
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Digital phase lock loop for jitter filtering and frequency offset compensation'
[patent_app_type] => 1
[patent_app_number] => 8/275795
[patent_app_country] => US
[patent_app_date] => 1994-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5516
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 390
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/469/05469478.pdf
[firstpage_image] =>[orig_patent_app_number] => 275795
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/275795 | Digital phase lock loop for jitter filtering and frequency offset compensation | Jul 14, 1994 | Issued |
Array
(
[id] => 3568000
[patent_doc_number] => 05502751
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-26
[patent_title] => 'Digital phase locked loop'
[patent_app_type] => 1
[patent_app_number] => 8/269245
[patent_app_country] => US
[patent_app_date] => 1994-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1232
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/502/05502751.pdf
[firstpage_image] =>[orig_patent_app_number] => 269245
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/269245 | Digital phase locked loop | Jun 29, 1994 | Issued |
Array
(
[id] => 3597831
[patent_doc_number] => 05553104
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal'
[patent_app_type] => 1
[patent_app_number] => 8/266779
[patent_app_country] => US
[patent_app_date] => 1994-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 7022
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/553/05553104.pdf
[firstpage_image] =>[orig_patent_app_number] => 266779
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/266779 | Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal | Jun 28, 1994 | Issued |