
Emmanuel E. Duke
Examiner (ID: 4116, Phone: (571)270-5290 , Office: P/3744 )
| Most Active Art Unit | 3763 |
| Art Unit(s) | 3763, 3744, 3784 |
| Total Applications | 1765 |
| Issued Applications | 1322 |
| Pending Applications | 81 |
| Abandoned Applications | 389 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3561742
[patent_doc_number] => 05502330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-26
[patent_title] => 'Stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link'
[patent_app_type] => 1
[patent_app_number] => 8/473865
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 2581
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/502/05502330.pdf
[firstpage_image] =>[orig_patent_app_number] => 473865
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/473865 | Stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link | Jun 6, 1995 | Issued |
Array
(
[id] => 3638139
[patent_doc_number] => 05610428
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-11
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/476221
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 3713
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/610/05610428.pdf
[firstpage_image] =>[orig_patent_app_number] => 476221
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/476221 | Semiconductor integrated circuit | Jun 6, 1995 | Issued |
Array
(
[id] => 3652781
[patent_doc_number] => 05684317
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'MOS transistor and method of manufacturing thereof'
[patent_app_type] => 1
[patent_app_number] => 8/483699
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 3946
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/684/05684317.pdf
[firstpage_image] =>[orig_patent_app_number] => 483699
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/483699 | MOS transistor and method of manufacturing thereof | Jun 6, 1995 | Issued |
Array
(
[id] => 3579697
[patent_doc_number] => 05523603
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Semiconductor device with reduced time-dependent dielectric failures'
[patent_app_type] => 1
[patent_app_number] => 8/472134
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3676
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/523/05523603.pdf
[firstpage_image] =>[orig_patent_app_number] => 472134
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/472134 | Semiconductor device with reduced time-dependent dielectric failures | Jun 6, 1995 | Issued |
| 08/472295 | MICROCOMPUTER WITH HIGH DENSITY RAM {IN SEPARATE ISOLATIONWELL} ON SINGLE CHIP | Jun 6, 1995 | Abandoned |
Array
(
[id] => 3661937
[patent_doc_number] => 05659188
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Capped anneal'
[patent_app_type] => 1
[patent_app_number] => 8/475724
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 3414
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/659/05659188.pdf
[firstpage_image] =>[orig_patent_app_number] => 475724
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/475724 | Capped anneal | Jun 6, 1995 | Issued |
Array
(
[id] => 3745039
[patent_doc_number] => 05753936
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Image forming member for electrophotography'
[patent_app_type] => 1
[patent_app_number] => 8/479856
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 14035
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/753/05753936.pdf
[firstpage_image] =>[orig_patent_app_number] => 479856
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/479856 | Image forming member for electrophotography | Jun 6, 1995 | Issued |
Array
(
[id] => 3893066
[patent_doc_number] => 05723897
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-03
[patent_title] => 'Segmented emitter low noise transistor'
[patent_app_type] => 1
[patent_app_number] => 8/484675
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2776
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/723/05723897.pdf
[firstpage_image] =>[orig_patent_app_number] => 484675
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/484675 | Segmented emitter low noise transistor | Jun 6, 1995 | Issued |
Array
(
[id] => 3707052
[patent_doc_number] => 05675164
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'High performance multi-mesa field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 8/486221
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 38
[patent_no_of_words] => 6130
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/675/05675164.pdf
[firstpage_image] =>[orig_patent_app_number] => 486221
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/486221 | High performance multi-mesa field effect transistor | Jun 6, 1995 | Issued |
Array
(
[id] => 3740762
[patent_doc_number] => 05698872
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Semiconductor memory wherein metallic interconnection layer is applied with the same potential as word line and is connected to word line in regions other than memory cells'
[patent_app_type] => 1
[patent_app_number] => 8/476905
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 3411
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 268
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/698/05698872.pdf
[firstpage_image] =>[orig_patent_app_number] => 476905
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/476905 | Semiconductor memory wherein metallic interconnection layer is applied with the same potential as word line and is connected to word line in regions other than memory cells | Jun 6, 1995 | Issued |
Array
(
[id] => 3583736
[patent_doc_number] => 05491357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-13
[patent_title] => 'Integrated structure current sensing resistor for power MOS devices, particularly for overload self-protected power MOS devices'
[patent_app_type] => 1
[patent_app_number] => 8/481198
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2359
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/491/05491357.pdf
[firstpage_image] =>[orig_patent_app_number] => 481198
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/481198 | Integrated structure current sensing resistor for power MOS devices, particularly for overload self-protected power MOS devices | Jun 6, 1995 | Issued |
Array
(
[id] => 3662989
[patent_doc_number] => 05592007
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'Membrane dielectric isolation transistor fabrication'
[patent_app_type] => 1
[patent_app_number] => 8/484029
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 64
[patent_figures_cnt] => 106
[patent_no_of_words] => 26698
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/592/05592007.pdf
[firstpage_image] =>[orig_patent_app_number] => 484029
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/484029 | Membrane dielectric isolation transistor fabrication | Jun 6, 1995 | Issued |
Array
(
[id] => 3857375
[patent_doc_number] => 05767544
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 8/470459
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 58
[patent_no_of_words] => 18197
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/767/05767544.pdf
[firstpage_image] =>[orig_patent_app_number] => 470459
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/470459 | Semiconductor integrated circuit device | Jun 5, 1995 | Issued |
| 08/466792 | SEMICONDUCTOR DEVICE AND METHOD FOR ITS PREPARATION | Jun 5, 1995 | Abandoned |
| 08/466105 | SEMICONDUCTOR DEVICE WITH MOISTURE IMPERVIOUS FILM | Jun 5, 1995 | Abandoned |
Array
(
[id] => 3788940
[patent_doc_number] => 05821624
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Semiconductor device assembly techniques using preformed planar structures'
[patent_app_type] => 1
[patent_app_number] => 8/470945
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 47
[patent_no_of_words] => 22380
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/821/05821624.pdf
[firstpage_image] =>[orig_patent_app_number] => 470945
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/470945 | Semiconductor device assembly techniques using preformed planar structures | Jun 4, 1995 | Issued |
Array
(
[id] => 3612324
[patent_doc_number] => 05589695
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'High-performance high-voltage device structures'
[patent_app_type] => 1
[patent_app_number] => 8/459369
[patent_app_country] => US
[patent_app_date] => 1995-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 13
[patent_no_of_words] => 2803
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/589/05589695.pdf
[firstpage_image] =>[orig_patent_app_number] => 459369
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/459369 | High-performance high-voltage device structures | Jun 1, 1995 | Issued |
Array
(
[id] => 3765922
[patent_doc_number] => 05742101
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/458166
[patent_app_country] => US
[patent_app_date] => 1995-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 3204
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 286
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/742/05742101.pdf
[firstpage_image] =>[orig_patent_app_number] => 458166
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/458166 | Semiconductor device | Jun 1, 1995 | Issued |
Array
(
[id] => 3835693
[patent_doc_number] => 05739564
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Semiconductor device having a static-random-access memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/460605
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 5674
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/739/05739564.pdf
[firstpage_image] =>[orig_patent_app_number] => 460605
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/460605 | Semiconductor device having a static-random-access memory cell | May 31, 1995 | Issued |
Array
(
[id] => 3594825
[patent_doc_number] => 05567985
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Electronic apparatus with compliant metal chip-substrate bonding layer(s)'
[patent_app_type] => 1
[patent_app_number] => 8/457551
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2343
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/567/05567985.pdf
[firstpage_image] =>[orig_patent_app_number] => 457551
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/457551 | Electronic apparatus with compliant metal chip-substrate bonding layer(s) | May 31, 1995 | Issued |