Search

Emmanuel E. Duke

Examiner (ID: 787, Phone: (571)270-5290 , Office: P/3744 )

Most Active Art Unit
3763
Art Unit(s)
3763, 3744, 3784
Total Applications
1762
Issued Applications
1322
Pending Applications
79
Abandoned Applications
388

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6827619 [patent_doc_number] => 20030178677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'STRAINED FIN FETS STRUCTURE AND METHOD' [patent_app_type] => new [patent_app_number] => 10/101807 [patent_app_country] => US [patent_app_date] => 2002-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 4805 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20030178677.pdf [firstpage_image] =>[orig_patent_app_number] => 10101807 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/101807
Strained fin FETs structure and method Mar 18, 2002 Issued
Array ( [id] => 1277807 [patent_doc_number] => 06645826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/093313 [patent_app_country] => US [patent_app_date] => 2002-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 95 [patent_no_of_words] => 20542 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/645/06645826.pdf [firstpage_image] =>[orig_patent_app_number] => 10093313 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/093313
Semiconductor device and method of fabricating the same Mar 6, 2002 Issued
Array ( [id] => 1316046 [patent_doc_number] => 06611026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Substrate-biased silicon diode for electrostatic discharge protection and fabrication method' [patent_app_type] => B2 [patent_app_number] => 10/092254 [patent_app_country] => US [patent_app_date] => 2002-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 32 [patent_no_of_words] => 5896 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611026.pdf [firstpage_image] =>[orig_patent_app_number] => 10092254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092254
Substrate-biased silicon diode for electrostatic discharge protection and fabrication method Mar 6, 2002 Issued
Array ( [id] => 1327980 [patent_doc_number] => 06603159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'System and methods for manufacturing and using a mask' [patent_app_type] => B2 [patent_app_number] => 10/053907 [patent_app_country] => US [patent_app_date] => 2002-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 15063 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603159.pdf [firstpage_image] =>[orig_patent_app_number] => 10053907 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/053907
System and methods for manufacturing and using a mask Jan 23, 2002 Issued
Array ( [id] => 1281477 [patent_doc_number] => 06646347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Semiconductor power device and method of formation' [patent_app_type] => B2 [patent_app_number] => 09/998507 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3797 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646347.pdf [firstpage_image] =>[orig_patent_app_number] => 09998507 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998507
Semiconductor power device and method of formation Nov 29, 2001 Issued
Array ( [id] => 6348661 [patent_doc_number] => 20020056837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Electro-optic device, drive substrate for electro-optic device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/993765 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 77 [patent_figures_cnt] => 77 [patent_no_of_words] => 26228 [patent_no_of_claims] => 172 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056837.pdf [firstpage_image] =>[orig_patent_app_number] => 09993765 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/993765
Electro-optic device, drive substrate for electro-optic device and method of manufacturing the same Nov 26, 2001 Issued
Array ( [id] => 1331960 [patent_doc_number] => 06596554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Body-tied-to-source partially depleted SOI MOSFET' [patent_app_type] => B2 [patent_app_number] => 09/994277 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2964 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596554.pdf [firstpage_image] =>[orig_patent_app_number] => 09994277 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994277
Body-tied-to-source partially depleted SOI MOSFET Nov 26, 2001 Issued
Array ( [id] => 1380256 [patent_doc_number] => 06563197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'MOSgated device termination with guard rings under field plate' [patent_app_type] => B1 [patent_app_number] => 09/989217 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1192 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563197.pdf [firstpage_image] =>[orig_patent_app_number] => 09989217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989217
MOSgated device termination with guard rings under field plate Nov 19, 2001 Issued
Array ( [id] => 1534598 [patent_doc_number] => 06410963 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Electrostatic discharge protection circuits with latch-up prevention function' [patent_app_type] => B1 [patent_app_number] => 09/977707 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3191 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410963.pdf [firstpage_image] =>[orig_patent_app_number] => 09977707 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977707
Electrostatic discharge protection circuits with latch-up prevention function Oct 15, 2001 Issued
Array ( [id] => 1419055 [patent_doc_number] => 06506645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Depletion compensated polysilicon electrodes' [patent_app_type] => B2 [patent_app_number] => 09/978137 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2872 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506645.pdf [firstpage_image] =>[orig_patent_app_number] => 09978137 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978137
Depletion compensated polysilicon electrodes Oct 14, 2001 Issued
Array ( [id] => 6603900 [patent_doc_number] => 20020064007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Low substrate-noise electrostatic discharge protection circuits with bi-directional silicon diodes' [patent_app_type] => new [patent_app_number] => 09/973745 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7384 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20020064007.pdf [firstpage_image] =>[orig_patent_app_number] => 09973745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973745
Low substrate-noise electrostatic discharge protection circuits with bi-directional silicon diodes Oct 10, 2001 Issued
Array ( [id] => 1424182 [patent_doc_number] => 06515324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Capacitor, capacitor mounting structure, method for manufacturing same, semiconductor device, and method for manufacturing same' [patent_app_type] => B2 [patent_app_number] => 09/942817 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11440 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515324.pdf [firstpage_image] =>[orig_patent_app_number] => 09942817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/942817
Capacitor, capacitor mounting structure, method for manufacturing same, semiconductor device, and method for manufacturing same Aug 29, 2001 Issued
Array ( [id] => 1424259 [patent_doc_number] => 06507074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Structure for ESD protection in semiconductor chips' [patent_app_type] => B2 [patent_app_number] => 09/945513 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1906 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507074.pdf [firstpage_image] =>[orig_patent_app_number] => 09945513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945513
Structure for ESD protection in semiconductor chips Aug 29, 2001 Issued
Array ( [id] => 6076007 [patent_doc_number] => 20020079531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Boride electrodes and barriers for cell dielectrics' [patent_app_type] => new [patent_app_number] => 09/941759 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2773 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20020079531.pdf [firstpage_image] =>[orig_patent_app_number] => 09941759 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941759
Boride electrodes and barriers for cell dielectrics Aug 29, 2001 Issued
Array ( [id] => 1272902 [patent_doc_number] => 06653721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'LOC semiconductor assembled with room temperature adhesive' [patent_app_type] => B2 [patent_app_number] => 09/942140 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2952 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653721.pdf [firstpage_image] =>[orig_patent_app_number] => 09942140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/942140
LOC semiconductor assembled with room temperature adhesive Aug 28, 2001 Issued
Array ( [id] => 1321416 [patent_doc_number] => 06605837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-12 [patent_title] => 'Memory cell configuration and production method' [patent_app_type] => B2 [patent_app_number] => 09/940087 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 8237 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/605/06605837.pdf [firstpage_image] =>[orig_patent_app_number] => 09940087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940087
Memory cell configuration and production method Aug 26, 2001 Issued
Array ( [id] => 1570102 [patent_doc_number] => 06498030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-24 [patent_title] => 'Surrounding-gate flash memory having a self-aligned control gate' [patent_app_type] => B2 [patent_app_number] => 09/925337 [patent_app_country] => US [patent_app_date] => 2001-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4504 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 408 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498030.pdf [firstpage_image] =>[orig_patent_app_number] => 09925337 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/925337
Surrounding-gate flash memory having a self-aligned control gate Aug 8, 2001 Issued
Array ( [id] => 1418346 [patent_doc_number] => 06514842 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Low resistance gate flash memory' [patent_app_type] => B1 [patent_app_number] => 09/924740 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 4599 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514842.pdf [firstpage_image] =>[orig_patent_app_number] => 09924740 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924740
Low resistance gate flash memory Aug 7, 2001 Issued
Array ( [id] => 1336838 [patent_doc_number] => 06597061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Card manufacturing technique and resulting card' [patent_app_type] => B1 [patent_app_number] => 09/921664 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2831 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597061.pdf [firstpage_image] =>[orig_patent_app_number] => 09921664 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921664
Card manufacturing technique and resulting card Aug 2, 2001 Issued
Array ( [id] => 6998451 [patent_doc_number] => 20010052629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Microlens for surface mount products' [patent_app_type] => new [patent_app_number] => 09/919231 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1526 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20010052629.pdf [firstpage_image] =>[orig_patent_app_number] => 09919231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919231
Microlens for surface mount products Jul 30, 2001 Issued
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