Enam Ahmed

Array ( [id] => 20101299 [patent_doc_number] => 20250231235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME [patent_app_type] => utility [patent_app_number] => 19/170909 [patent_app_country] => US [patent_app_date] => 2025-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19170909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20250889 [patent_doc_number] => 20250299758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => SCAN OPERATIONS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 19/048338 [patent_app_country] => US [patent_app_date] => 2025-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19048338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20101898 [patent_doc_number] => 20250231834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => FAILURE COUNT-BASED READ ERROR HANDLING USING LLR DATA [patent_app_type] => utility [patent_app_number] => 19/013584 [patent_app_country] => US [patent_app_date] => 2025-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20095093 [patent_doc_number] => 20250225029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => MEMORY DEVICE DECODING USING RELIABILITY VALUES [patent_app_type] => utility [patent_app_number] => 19/011010 [patent_app_country] => US [patent_app_date] => 2025-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19011010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20783941 [patent_doc_number] => 20260172144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-18 [patent_title] => STATE REDUCTION FOR SEQUENCE ESTIMATION BASED ON SIGNAL QUALITY [patent_app_type] => utility [patent_app_number] => 18/982935 [patent_app_country] => US [patent_app_date] => 2024-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18982935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20221657 [patent_doc_number] => 20250284588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => DECODER CIRCUIT, FLASH MEMORY CONTROLLER, AND DECODING METHOD [patent_app_type] => utility [patent_app_number] => 18/950158 [patent_app_country] => US [patent_app_date] => 2024-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18950158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20036069 [patent_doc_number] => 20250174291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => Memory apparatus having at-speed test mechanism and memory test method of the same [patent_app_type] => utility [patent_app_number] => 18/948580 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19758846 [patent_doc_number] => 20250047411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => MULTI-STAGE ENCODING AND MULTI-STAGE DECODING OF INFORMATION BITS [patent_app_type] => utility [patent_app_number] => 18/927513 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18927513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20661005 [patent_doc_number] => 20260113059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => DECODING APPARATUS AND METHOD IN WIRELESS COMMUNICATION NETWORK [patent_app_type] => utility [patent_app_number] => 18/923489 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 436 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20658694 [patent_doc_number] => 20260110735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => INTEGRATED PROTOCOL ANALYZER CONFIGURED WITHIN AUTOMATED TEST EQUIPMENT (ATE) HARDWARE WITH SIDEBAND AND SYSTEM EVENT TRIGGERING AND MEMORY POOLING [patent_app_type] => utility [patent_app_number] => 18/921766 [patent_app_country] => US [patent_app_date] => 2024-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18921766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20018049 [patent_doc_number] => 20250156271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SYNDROME CALCULATION [patent_app_type] => utility [patent_app_number] => 18/913708 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20652942 [patent_doc_number] => 20260104961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => HARD INFORMATION DECODER AIDED BY A SOFT INFORMATION DECODER [patent_app_type] => utility [patent_app_number] => 18/913707 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19893924 [patent_doc_number] => 20250119236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => INTERFACE DEVICE FOR MULTIPLEXING MULTIPLE NETWORK PORTS OVER SINGLE SERDES [patent_app_type] => utility [patent_app_number] => 18/908669 [patent_app_country] => US [patent_app_date] => 2024-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20635737 [patent_doc_number] => 12596611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Memory system and memory management method thereof [patent_app_type] => utility [patent_app_number] => 18/802199 [patent_app_country] => US [patent_app_date] => 2024-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18802199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20851055 [patent_doc_number] => 12688087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-21 [patent_title] => Probablistically determining memory portions for select gate scanning [patent_app_type] => utility [patent_app_number] => 18/790947 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2243 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790947 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20070728 [patent_doc_number] => 20250208950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => MEMORY MAINTENANCE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/791126 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20717084 [patent_doc_number] => 12632335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Data storage system with adaptive flash media scan [patent_app_type] => utility [patent_app_number] => 18/789309 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19891977 [patent_doc_number] => 20250117289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => VALLEY CHECK MEMORY SYSTEM COMMAND [patent_app_type] => utility [patent_app_number] => 18/788550 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20513268 [patent_doc_number] => 20260037369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => HANDLING READ FAILURE IN ZONE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/788474 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20746651 [patent_doc_number] => 12646570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory [patent_app_type] => utility [patent_app_number] => 18/784972 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 14416 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784972 [rel_patent_id] =>[rel_patent_doc_number] =>)