Search

Enam Ahmed

Examiner (ID: 10807, Phone: (571)270-1729 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112
Total Applications
834
Issued Applications
668
Pending Applications
34
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16242272 [patent_doc_number] => 20200259506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => ERROR TRAPPING IN MEMORY STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/273370 [patent_app_country] => US [patent_app_date] => 2019-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16273370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/273370
Error trapping in memory structures Feb 11, 2019 Issued
Array ( [id] => 16651274 [patent_doc_number] => 10928446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Watchdog built in test (BIT) circuit for fast system readiness [patent_app_type] => utility [patent_app_number] => 16/261648 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3865 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261648 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/261648
Watchdog built in test (BIT) circuit for fast system readiness Jan 29, 2019 Issued
Array ( [id] => 16565820 [patent_doc_number] => 10891189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Customized parameterization of read parameters after a decoding failure for solid state storage devices [patent_app_type] => utility [patent_app_number] => 16/259346 [patent_app_country] => US [patent_app_date] => 2019-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 9020 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/259346
Customized parameterization of read parameters after a decoding failure for solid state storage devices Jan 27, 2019 Issued
Array ( [id] => 17225394 [patent_doc_number] => 11177909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Methods and apparatus related to ACK/NACK feedback with multi-TRP transmissions [patent_app_type] => utility [patent_app_number] => 16/258265 [patent_app_country] => US [patent_app_date] => 2019-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 19383 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16258265 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/258265
Methods and apparatus related to ACK/NACK feedback with multi-TRP transmissions Jan 24, 2019 Issued
Array ( [id] => 16789871 [patent_doc_number] => 10992314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Residue number systems and methods for arithmetic error detection and correction [patent_app_type] => utility [patent_app_number] => 16/253119 [patent_app_country] => US [patent_app_date] => 2019-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 37 [patent_no_of_words] => 20439 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16253119 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/253119
Residue number systems and methods for arithmetic error detection and correction Jan 20, 2019 Issued
Array ( [id] => 16192894 [patent_doc_number] => 20200233743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => ERROR CORRECTION CODE MEMORY DEVICE AND CODEWORD ACCESSING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/251090 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251090 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/251090
Error correction code memory device and codeword accessing method thereof Jan 17, 2019 Issued
Array ( [id] => 14318943 [patent_doc_number] => 20190149175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 16/244627 [patent_app_country] => US [patent_app_date] => 2019-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16244627 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/244627
Stopping criteria for layered iterative error correction Jan 9, 2019 Issued
Array ( [id] => 14570931 [patent_doc_number] => 20190213072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => MEMORY SYSTEM WITH SUPER CHIP-KILL RECOVERY AND METHOD OF OPERATING SUCH MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/238370 [patent_app_country] => US [patent_app_date] => 2019-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16238370 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/238370
Memory system with super chip-kill recovery and method of operating such memory system Jan 1, 2019 Issued
Array ( [id] => 16116531 [patent_doc_number] => 20200210288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SYSTEM AND METHOD FOR FACILITATING DIFFERENTIATED ERROR CORRECTION IN HIGH-DENSITY FLASH DEVICES [patent_app_type] => utility [patent_app_number] => 16/237340 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237340 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237340
System and method for facilitating differentiated error correction in high-density flash devices Dec 30, 2018 Issued
Array ( [id] => 16879736 [patent_doc_number] => 11029883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Reduce system active power based on memory usage patterns [patent_app_type] => utility [patent_app_number] => 16/484066 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10860 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16484066 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/484066
Reduce system active power based on memory usage patterns Dec 27, 2018 Issued
Array ( [id] => 16338160 [patent_doc_number] => 10789116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Method for determining location where memory error occurs [patent_app_type] => utility [patent_app_number] => 16/220108 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5141 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220108 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/220108
Method for determining location where memory error occurs Dec 13, 2018 Issued
Array ( [id] => 14222763 [patent_doc_number] => 20190123766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => METHOD FOR DETERMINING A DECODING TASK AND APPARATUS [patent_app_type] => utility [patent_app_number] => 16/219465 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219465 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219465
Method for determining a decoding task and apparatus Dec 12, 2018 Issued
Array ( [id] => 16355252 [patent_doc_number] => 10795763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Memory system and error correcting method thereof [patent_app_type] => utility [patent_app_number] => 16/203862 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4753 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203862 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203862
Memory system and error correcting method thereof Nov 28, 2018 Issued
Array ( [id] => 16772877 [patent_doc_number] => 10983985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Determining a storage pool to store changed data objects indicated in a database [patent_app_type] => utility [patent_app_number] => 16/174272 [patent_app_country] => US [patent_app_date] => 2018-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8157 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16174272 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/174272
Determining a storage pool to store changed data objects indicated in a database Oct 28, 2018 Issued
Array ( [id] => 15171617 [patent_doc_number] => 10491326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Method and apparatus for encoding data using a polar code [patent_app_type] => utility [patent_app_number] => 16/163253 [patent_app_country] => US [patent_app_date] => 2018-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 42 [patent_no_of_words] => 21131 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16163253 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/163253
Method and apparatus for encoding data using a polar code Oct 16, 2018 Issued
Array ( [id] => 13880415 [patent_doc_number] => 20190036548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => PERMUTATION NETWORK DESIGNING METHOD, AND PERMUTATION CIRCUIT OF QC-LDPC DECODER [patent_app_type] => utility [patent_app_number] => 16/145213 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145213 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145213
Permutation network designing method, and permutation circuit of QC-LDPC decoder Sep 27, 2018 Issued
Array ( [id] => 14025713 [patent_doc_number] => 20190074850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => PERMUTATION NETWORK DESIGNING METHOD, AND PERMUTATION CIRCUIT OF QC-LDPC DECODER [patent_app_type] => utility [patent_app_number] => 16/145207 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 423 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145207 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145207
Permutation network designing method, and permutation circuit of QC-LDPC decoder Sep 27, 2018 Issued
Array ( [id] => 14676077 [patent_doc_number] => 20190237153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/123514 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123514 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/123514
Semiconductor memory device and operating method Sep 5, 2018 Issued
Array ( [id] => 14107195 [patent_doc_number] => 20190095273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => PARITY BITS LOCATION ON I3C MULTILANE BUS [patent_app_type] => utility [patent_app_number] => 16/123737 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123737 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/123737
PARITY BITS LOCATION ON I3C MULTILANE BUS Sep 5, 2018 Abandoned
Array ( [id] => 15624993 [patent_doc_number] => 20200082901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => MEMORY SUB-SYSTEM INCLUDING AN IN-PACKAGE SEQUENCER TO PERFORM ERROR CORRECTION AND MEMORY TESTING OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/123911 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/123911
Memory sub-system including an in-package sequencer to perform error correction and memory testing operations Sep 5, 2018 Issued
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