Search

Enam Ahmed

Examiner (ID: 10807, Phone: (571)270-1729 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112
Total Applications
834
Issued Applications
668
Pending Applications
34
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20208610 [patent_doc_number] => 20250278330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => Low latency crosstalk mitigation in a nonvolatile memory [patent_app_type] => utility [patent_app_number] => 18/779122 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779122
Low latency crosstalk mitigation in a nonvolatile memory Jul 21, 2024 Issued
Array ( [id] => 19848927 [patent_doc_number] => 20250094278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => RAS TRIGGERS L2P TABLE MOVEMENT IN CXL DEVICES WITH COMPRESSION [patent_app_type] => utility [patent_app_number] => 18/778665 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778665 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778665
RAS triggers L2P table movement in CXL devices with compression Jul 18, 2024 Issued
Array ( [id] => 19787341 [patent_doc_number] => 20250061020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => TRACKING LATCH UPSET EVENTS USING A TRIM REGISTER [patent_app_type] => utility [patent_app_number] => 18/778645 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778645
TRACKING LATCH UPSET EVENTS USING A TRIM REGISTER Jul 18, 2024 Pending
Array ( [id] => 19558543 [patent_doc_number] => 20240370335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/778475 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778475 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778475
SEMICONDUCTOR MEMORY DEVICES Jul 18, 2024 Abandoned
Array ( [id] => 20717083 [patent_doc_number] => 12632334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Data transmission system, verification method and slave device [patent_app_type] => utility [patent_app_number] => 18/772297 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772297 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772297
Data transmission system, verification method and slave device Jul 14, 2024 Issued
Array ( [id] => 20296028 [patent_doc_number] => 20250321271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => SYSTEM AND METHOD FOR DEVELOPING AND DEBUGGING A SILICON PRODUCTION TEST PROGRAM FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/733701 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733701 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733701
System and method for developing and debugging a silicon production test program for semiconductor devices Jun 3, 2024 Issued
Array ( [id] => 20273704 [patent_doc_number] => 12443486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Evaluation of memory device health monitoring logic [patent_app_type] => utility [patent_app_number] => 18/680470 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16741 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680470 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680470
Evaluation of memory device health monitoring logic May 30, 2024 Issued
Array ( [id] => 19605693 [patent_doc_number] => 20240396573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => ASSOCIATIVE COMPUTING FOR ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/679022 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679022 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679022
ASSOCIATIVE COMPUTING FOR ERROR CORRECTION May 29, 2024 Issued
Array ( [id] => 20365950 [patent_doc_number] => 20250355762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => Data Storage Device and Method for Generating Read Threshold Voltages [patent_app_type] => utility [patent_app_number] => 18/664514 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664514 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664514
Data Storage Device and Method for Generating Read Threshold Voltages May 14, 2024 Pending
Array ( [id] => 20070727 [patent_doc_number] => 20250208949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => ERROR CORRECTION CODE ENGINE OF SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/660589 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660589 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660589
Error correction code engine of semiconductor memory device and semiconductor memory device May 9, 2024 Issued
Array ( [id] => 20716922 [patent_doc_number] => 12632172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Self-corrected low-density parity check (LDPC) with index match [patent_app_type] => utility [patent_app_number] => 18/656418 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656418
Self-corrected low-density parity check (LDPC) with index match May 5, 2024 Issued
Array ( [id] => 20704061 [patent_doc_number] => 12626776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/639372 [patent_app_country] => US [patent_app_date] => 2024-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639372 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/639372
Semiconductor memory device Apr 17, 2024 Issued
Array ( [id] => 20403546 [patent_doc_number] => 12493519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Hardware memory error tolerant software system [patent_app_type] => utility [patent_app_number] => 18/594656 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4468 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594656
Hardware memory error tolerant software system Mar 3, 2024 Issued
Array ( [id] => 20456425 [patent_doc_number] => 12519488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => System and method for generation of error-correcting codes in communication systems [patent_app_type] => utility [patent_app_number] => 18/594222 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6749 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 573 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594222 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594222
System and method for generation of error-correcting codes in communication systems Mar 3, 2024 Issued
Array ( [id] => 19466439 [patent_doc_number] => 20240320109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/590795 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590795
SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF SEMICONDUCTOR MEMORY DEVICE Feb 27, 2024 Pending
Array ( [id] => 19819142 [patent_doc_number] => 20250077349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => MEMORY DEVICE ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/430287 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430287 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430287
MEMORY DEVICE ERROR CORRECTION Jan 31, 2024 Pending
Array ( [id] => 20529052 [patent_doc_number] => 12547487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Electronic system and method of managing errors of the same [patent_app_type] => utility [patent_app_number] => 18/430328 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 11589 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430328 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430328
Electronic system and method of managing errors of the same Jan 31, 2024 Issued
Array ( [id] => 20101894 [patent_doc_number] => 20250231830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => BEST HEDGING, UTILIZATION AND VALIDATION OF INFORMATION (BHUVI) MACHINE LEARNING MODEL [patent_app_type] => utility [patent_app_number] => 18/411161 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411161
BEST HEDGING, UTILIZATION AND VALIDATION OF INFORMATION (BHUVI) MACHINE LEARNING MODEL Jan 11, 2024 Pending
Array ( [id] => 20259551 [patent_doc_number] => 12431918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Rate matching methods for LDPC codes [patent_app_type] => utility [patent_app_number] => 18/390349 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6884 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390349 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/390349
Rate matching methods for LDPC codes Dec 19, 2023 Issued
Array ( [id] => 20259551 [patent_doc_number] => 12431918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Rate matching methods for LDPC codes [patent_app_type] => utility [patent_app_number] => 18/390349 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6884 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390349 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/390349
Rate matching methods for LDPC codes Dec 19, 2023 Issued
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