Search

Eret C. Mcnichols

Examiner (ID: 4703, Phone: (571)270-7363 , Office: P/3632 )

Most Active Art Unit
3632
Art Unit(s)
3632
Total Applications
997
Issued Applications
702
Pending Applications
93
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20009673 [patent_doc_number] => 20250147895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => PROGRAM PROCESSING DEVICE AND PROGRAM PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 19/015883 [patent_app_country] => US [patent_app_date] => 2025-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19015883 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/015883
PROGRAM PROCESSING DEVICE AND PROGRAM PROCESSING METHOD Jan 9, 2025 Pending
Array ( [id] => 20221470 [patent_doc_number] => 20250284401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => MEMORY SYSTEM AND METHOD OF MANAGING ADDRESSES OF A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 19/013590 [patent_app_country] => US [patent_app_date] => 2025-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013590 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/013590
MEMORY SYSTEM AND METHOD OF MANAGING ADDRESSES OF A MEMORY SYSTEM Jan 7, 2025 Pending
Array ( [id] => 19985537 [patent_doc_number] => 20250123759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => TECHNIQUES TO PREDICT OR DETERMINE TIME-TO-READY FOR A STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/984383 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18984383 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/984383
TECHNIQUES TO PREDICT OR DETERMINE TIME-TO-READY FOR A STORAGE DEVICE Dec 16, 2024 Pending
Array ( [id] => 20034851 [patent_doc_number] => 20250173073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => STORAGE SYSTEM AND A METHOD OF CONTROLLING ENERGY CONSUMPTION THEREIN [patent_app_type] => utility [patent_app_number] => 18/978311 [patent_app_country] => US [patent_app_date] => 2024-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18978311 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/978311
STORAGE SYSTEM AND A METHOD OF CONTROLLING ENERGY CONSUMPTION THEREIN Dec 11, 2024 Pending
Array ( [id] => 19848697 [patent_doc_number] => 20250094048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => Data Access Method and Apparatus, and First Computing Device [patent_app_type] => utility [patent_app_number] => 18/962213 [patent_app_country] => US [patent_app_date] => 2024-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18962213 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/962213
Data Access Method and Apparatus, and First Computing Device Nov 26, 2024 Pending
Array ( [id] => 20009457 [patent_doc_number] => 20250147679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => LIGHT HIBERNATION MODE FOR MEMORY [patent_app_type] => utility [patent_app_number] => 18/947633 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18947633 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/947633
LIGHT HIBERNATION MODE FOR MEMORY Nov 13, 2024 Pending
Array ( [id] => 19771875 [patent_doc_number] => 20250053301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/929570 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18929570 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/929570
PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEMORY DEVICE Oct 27, 2024 Pending
Array ( [id] => 19756410 [patent_doc_number] => 20250044975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => QUICK CLEARING OF REGISTERS [patent_app_type] => utility [patent_app_number] => 18/921096 [patent_app_country] => US [patent_app_date] => 2024-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18921096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/921096
QUICK CLEARING OF REGISTERS Oct 20, 2024 Pending
Array ( [id] => 20000519 [patent_doc_number] => 20250138741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SEMICONDUCTOR DEVICE AND WRITING METHOD [patent_app_type] => utility [patent_app_number] => 18/921336 [patent_app_country] => US [patent_app_date] => 2024-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18921336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/921336
SEMICONDUCTOR DEVICE AND WRITING METHOD Oct 20, 2024 Pending
Array ( [id] => 20481673 [patent_doc_number] => 12530148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Memory controller circuit and system for artificial neural network and method thereof [patent_app_type] => utility [patent_app_number] => 18/908844 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 63 [patent_no_of_words] => 50718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/908844
Memory controller circuit and system for artificial neural network and method thereof Oct 7, 2024 Issued
Array ( [id] => 19617228 [patent_doc_number] => 20240402908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => METHOD OF FORMING FERROELECTRIC CHIPLET IN A MULTI-DIMENSIONAL PACKAGING WITH I/O SWITCH EMBEDDED IN A SUBSTRATE OR INTERPOSER [patent_app_type] => utility [patent_app_number] => 18/806592 [patent_app_country] => US [patent_app_date] => 2024-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18806592 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/806592
METHOD OF FORMING FERROELECTRIC CHIPLET IN A MULTI-DIMENSIONAL PACKAGING WITH I/O SWITCH EMBEDDED IN A SUBSTRATE OR INTERPOSER Aug 14, 2024 Pending
Array ( [id] => 19603067 [patent_doc_number] => 20240393947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => Method for Adjusting Specification Parameter of SSD and Related Product [patent_app_type] => utility [patent_app_number] => 18/796930 [patent_app_country] => US [patent_app_date] => 2024-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18796930 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/796930
Method for Adjusting Specification Parameter of SSD and Related Product Aug 6, 2024 Pending
Array ( [id] => 19756404 [patent_doc_number] => 20250044969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => OPTICAL COMPUTING WITH DISAGGREGATED MEMORY [patent_app_type] => utility [patent_app_number] => 18/793079 [patent_app_country] => US [patent_app_date] => 2024-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18793079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/793079
Optical computing with disaggregated memory Aug 1, 2024 Issued
Array ( [id] => 20026946 [patent_doc_number] => 20250165168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => METHOD AND SYSTEM FOR DYNAMIC STORAGE SCALING [patent_app_type] => utility [patent_app_number] => 18/789506 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789506 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789506
METHOD AND SYSTEM FOR DYNAMIC STORAGE SCALING Jul 29, 2024 Pending
Array ( [id] => 20487290 [patent_doc_number] => 20260023489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => STORAGE USAGE [patent_app_type] => utility [patent_app_number] => 18/778203 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778203 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778203
STORAGE USAGE Jul 18, 2024 Issued
Array ( [id] => 20474731 [patent_doc_number] => 20260016952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => KV CACHE BLOCK-QUANTIZATION ORIENTED DATA HANDLING [patent_app_type] => utility [patent_app_number] => 18/772712 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772712 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772712
KV CACHE BLOCK-QUANTIZATION ORIENTED DATA HANDLING Jul 14, 2024 Pending
Array ( [id] => 20434208 [patent_doc_number] => 12504889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Memory management method for evenly distributing input output latency time, memory storage device, and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 18/760043 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2133 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760043
Memory management method for evenly distributing input output latency time, memory storage device, and memory control circuit unit Jun 30, 2024 Issued
Array ( [id] => 19878386 [patent_doc_number] => 20250110643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => APPARATUSES AND METHODS FOR BOUNDED FAULT COMPLIANT METADATA STORAGE [patent_app_type] => utility [patent_app_number] => 18/747658 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747658 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747658
APPARATUSES AND METHODS FOR BOUNDED FAULT COMPLIANT METADATA STORAGE Jun 18, 2024 Pending
Array ( [id] => 19466240 [patent_doc_number] => 20240319910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Alleviating Interconnect Traffic in a Disaggregated Memory System [patent_app_type] => utility [patent_app_number] => 18/731056 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731056
Alleviating Interconnect Traffic in a Disaggregated Memory System May 30, 2024 Abandoned
Array ( [id] => 19466241 [patent_doc_number] => 20240319911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Alleviating Interconnect Traffic in a Disaggregated Memory System [patent_app_type] => utility [patent_app_number] => 18/731089 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731089
Alleviating interconnect traffic in a disaggregated memory system May 30, 2024 Issued
Menu