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Eric A. Ward

Examiner (ID: 5402)

Most Active Art Unit
2891
Art Unit(s)
2891
Total Applications
925
Issued Applications
670
Pending Applications
71
Abandoned Applications
202

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17723531 [patent_doc_number] => 20220216253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => CAPACITANCE MATCHED METAL WIRINGS IN DUAL CONVERSION GAIN PIXELS [patent_app_type] => utility [patent_app_number] => 17/610264 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17610264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/610264
Capacitance matched metal wirings in dual conversion gain pixels May 20, 2020 Issued
Array ( [id] => 17738175 [patent_doc_number] => 20220223637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/609960 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17609960 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/609960
SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF May 19, 2020 Abandoned
Array ( [id] => 16456394 [patent_doc_number] => 20200365820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => ORGANIC EL ELEMENT, ORGANIC EL DISPLAY PANEL, AND MANUFACTURING METHOD OF ORGANIC EL ELEMENT [patent_app_type] => utility [patent_app_number] => 16/874791 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874791 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874791
ORGANIC EL ELEMENT, ORGANIC EL DISPLAY PANEL, AND MANUFACTURING METHOD OF ORGANIC EL ELEMENT May 14, 2020 Abandoned
Array ( [id] => 16456306 [patent_doc_number] => 20200365732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/874033 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874033 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874033
Field effect transistor May 13, 2020 Issued
Array ( [id] => 17232535 [patent_doc_number] => 20210359092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => LAYOUT TECHNIQUES AND OPTIMIZATION FOR POWER TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/874098 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874098 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874098
Layout techniques and optimization for power transistors May 13, 2020 Issued
Array ( [id] => 19766046 [patent_doc_number] => 12224349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Self-aligned gate endcap (SAGE) architectures with vertical sidewalls [patent_app_type] => utility [patent_app_number] => 16/868828 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 12415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868828
Self-aligned gate endcap (SAGE) architectures with vertical sidewalls May 6, 2020 Issued
Array ( [id] => 17847981 [patent_doc_number] => 11437367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Heterogeneous integrated wideband high electron mobility transistor power amplifier with a single-crystal acoustic resonator/filter [patent_app_type] => utility [patent_app_number] => 16/854313 [patent_app_country] => US [patent_app_date] => 2020-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 8816 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854313 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/854313
Heterogeneous integrated wideband high electron mobility transistor power amplifier with a single-crystal acoustic resonator/filter Apr 20, 2020 Issued
Array ( [id] => 17551764 [patent_doc_number] => 20220123106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/766710 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16766710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/766710
III-nitride semiconductor device with non-active regions to shape 2DEG layer Apr 12, 2020 Issued
Array ( [id] => 16566985 [patent_doc_number] => 10892362 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-12 [patent_title] => Devices for LDMOS and other MOS transistors with hybrid contact [patent_app_type] => utility [patent_app_number] => 16/845666 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 10252 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845666 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845666
Devices for LDMOS and other MOS transistors with hybrid contact Apr 9, 2020 Issued
Array ( [id] => 16348328 [patent_doc_number] => 20200312979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => Silicon Carbide Device with Trench Gate Structure and Method of Manufacturing [patent_app_type] => utility [patent_app_number] => 16/832653 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/832653
Silicon carbide device with trench gate structure and method of manufacturing Mar 26, 2020 Issued
Array ( [id] => 17130622 [patent_doc_number] => 20210305391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => METAL SEMICONDUCTOR CONTACTS [patent_app_type] => utility [patent_app_number] => 16/831746 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831746 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831746
Metal semiconductor contacts Mar 25, 2020 Issued
Array ( [id] => 16180329 [patent_doc_number] => 20200227298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => METHOD FOR ALIGNMENT, PROCESS TOOL AND METHOD FOR WAFER-LEVEL ALIGNMENT [patent_app_type] => utility [patent_app_number] => 16/829248 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829248 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/829248
Method for alignment, process tool and method for wafer-level alignment Mar 24, 2020 Issued
Array ( [id] => 16163517 [patent_doc_number] => 20200219991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/824339 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824339 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/824339
Semiconductor device including two thin-film transistors and method of fabricating the same Mar 18, 2020 Issued
Array ( [id] => 18256282 [patent_doc_number] => 20230083321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => Voltage Current Conversion Device [patent_app_type] => utility [patent_app_number] => 17/907870 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17907870 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/907870
Voltage Current Conversion Device Mar 17, 2020 Abandoned
Array ( [id] => 18797103 [patent_doc_number] => 11830940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Semiconductor device including high electron mobility transistor or high hole mobility transistor and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/811898 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 8891 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811898 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/811898
Semiconductor device including high electron mobility transistor or high hole mobility transistor and method of fabricating the same Mar 5, 2020 Issued
Array ( [id] => 16715800 [patent_doc_number] => 20210082947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/800214 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/800214
Memory device Feb 24, 2020 Issued
Array ( [id] => 17284194 [patent_doc_number] => 11201238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Semiconductor device, method of manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator [patent_app_type] => utility [patent_app_number] => 16/797048 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 9828 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 375 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797048 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/797048
Semiconductor device, method of manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator Feb 20, 2020 Issued
Array ( [id] => 17055852 [patent_doc_number] => 20210265286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => CHIP CORNER AREAS WITH A DUMMY FILL PATTERN [patent_app_type] => utility [patent_app_number] => 16/796372 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796372 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796372
Chip corner areas with a dummy fill pattern Feb 19, 2020 Issued
Array ( [id] => 16528731 [patent_doc_number] => 20200402812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/796667 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796667 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796667
Semiconductor device with dummy gate and metal gate and method of fabricating the same Feb 19, 2020 Issued
Array ( [id] => 17787862 [patent_doc_number] => 11410998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => LDMOS finFET structure with buried insulator layer and method for forming same [patent_app_type] => utility [patent_app_number] => 16/796326 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 7130 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796326 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796326
LDMOS finFET structure with buried insulator layer and method for forming same Feb 19, 2020 Issued
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