Search

Eric Cardwell

Examiner (ID: 15663, Phone: (571)270-1379 , Office: P/2131 )

Most Active Art Unit
2139
Art Unit(s)
2189, 2139, 2131
Total Applications
763
Issued Applications
646
Pending Applications
50
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5122041 [patent_doc_number] => 20070143756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'System and method for performing time-flexible calendric storage operations' [patent_app_type] => utility [patent_app_number] => 11/313225 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8352 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143756.pdf [firstpage_image] =>[orig_patent_app_number] => 11313225 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313225
System and method for performing time-flexible calendric storage operations Dec 18, 2005 Issued
Array ( [id] => 192925 [patent_doc_number] => 07644251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Non-volatile solid-state memory controller' [patent_app_type] => utility [patent_app_number] => 11/312852 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6847 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/644/07644251.pdf [firstpage_image] =>[orig_patent_app_number] => 11312852 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/312852
Non-volatile solid-state memory controller Dec 18, 2005 Issued
Array ( [id] => 321250 [patent_doc_number] => 07523264 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-21 [patent_title] => 'Apparatus, system, and method for dependent computations of streaming multiprocessors' [patent_app_type] => utility [patent_app_number] => 11/303770 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523264.pdf [firstpage_image] =>[orig_patent_app_number] => 11303770 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/303770
Apparatus, system, and method for dependent computations of streaming multiprocessors Dec 14, 2005 Issued
Array ( [id] => 321310 [patent_doc_number] => 07523282 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-21 [patent_title] => 'Clock enable throttling for power savings in a memory subsystem' [patent_app_type] => utility [patent_app_number] => 11/260416 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6057 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523282.pdf [firstpage_image] =>[orig_patent_app_number] => 11260416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260416
Clock enable throttling for power savings in a memory subsystem Oct 26, 2005 Issued
Array ( [id] => 208462 [patent_doc_number] => 07631162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Non-volatile memory with adaptive handling of data writes' [patent_app_type] => utility [patent_app_number] => 11/261150 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 14558 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/631/07631162.pdf [firstpage_image] =>[orig_patent_app_number] => 11261150 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261150
Non-volatile memory with adaptive handling of data writes Oct 26, 2005 Issued
Array ( [id] => 283935 [patent_doc_number] => 07555625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Multi-memory chip and data transfer method capable of directly transferring data between internal memory devices' [patent_app_type] => utility [patent_app_number] => 11/260008 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5295 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/555/07555625.pdf [firstpage_image] =>[orig_patent_app_number] => 11260008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260008
Multi-memory chip and data transfer method capable of directly transferring data between internal memory devices Oct 26, 2005 Issued
Array ( [id] => 5036556 [patent_doc_number] => 20070101095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Methods for adaptively handling data writes in non-volatile memories' [patent_app_type] => utility [patent_app_number] => 11/261138 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14549 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101095.pdf [firstpage_image] =>[orig_patent_app_number] => 11261138 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261138
Methods for adaptively handling data writes in non-volatile memories Oct 26, 2005 Issued
Array ( [id] => 5036528 [patent_doc_number] => 20070101067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'System and method for contention-based cache performance optimization' [patent_app_type] => utility [patent_app_number] => 11/260555 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5679 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101067.pdf [firstpage_image] =>[orig_patent_app_number] => 11260555 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260555
System and method for contention-based cache performance optimization Oct 26, 2005 Issued
Array ( [id] => 5036529 [patent_doc_number] => 20070101068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'System and method for memory coherence protocol enhancement using cache line access frequencies' [patent_app_type] => utility [patent_app_number] => 11/260833 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101068.pdf [firstpage_image] =>[orig_patent_app_number] => 11260833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260833
Memory coherence protocol enhancement using cache line access frequencies Oct 26, 2005 Issued
Array ( [id] => 5927691 [patent_doc_number] => 20060242283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'System and method for managing local storage resources to reduce I/O demand in a storage area network' [patent_app_type] => utility [patent_app_number] => 11/231668 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242283.pdf [firstpage_image] =>[orig_patent_app_number] => 11231668 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/231668
System and method for managing local storage resources to reduce I/O demand in a storage area network Sep 20, 2005 Abandoned
Array ( [id] => 5603963 [patent_doc_number] => 20060294310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Write control method and storage apparatus' [patent_app_type] => utility [patent_app_number] => 11/231404 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3591 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20060294310.pdf [firstpage_image] =>[orig_patent_app_number] => 11231404 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/231404
Write control method and storage apparatus Sep 20, 2005 Abandoned
Array ( [id] => 604812 [patent_doc_number] => 07434012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-07 [patent_title] => 'Techniques for media scrubbing' [patent_app_type] => utility [patent_app_number] => 11/231730 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/434/07434012.pdf [firstpage_image] =>[orig_patent_app_number] => 11231730 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/231730
Techniques for media scrubbing Sep 20, 2005 Issued
Array ( [id] => 371913 [patent_doc_number] => 07478196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Firmware enabled trap-based RAID implementation' [patent_app_type] => utility [patent_app_number] => 11/231944 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4061 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/478/07478196.pdf [firstpage_image] =>[orig_patent_app_number] => 11231944 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/231944
Firmware enabled trap-based RAID implementation Sep 20, 2005 Issued
Array ( [id] => 5108691 [patent_doc_number] => 20070067569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Method and system for communicating validation information to a web cache' [patent_app_type] => utility [patent_app_number] => 11/232583 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4215 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20070067569.pdf [firstpage_image] =>[orig_patent_app_number] => 11232583 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/232583
Method and system for communicating validation information to a web cache Sep 20, 2005 Abandoned
Array ( [id] => 5765070 [patent_doc_number] => 20060018154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Partial permanent write protection of a memory card and partially permanently write protected memory card' [patent_app_type] => utility [patent_app_number] => 11/176669 [patent_app_country] => US [patent_app_date] => 2005-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2378 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20060018154.pdf [firstpage_image] =>[orig_patent_app_number] => 11176669 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/176669
Partial permanent write protection of a memory card and partially permanently write protected memory card Jul 7, 2005 Issued
Array ( [id] => 4996061 [patent_doc_number] => 20070011406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Systems and methods for increasing yield of devices having cache memories by inhibiting use of defective cache entries' [patent_app_type] => utility [patent_app_number] => 11/175504 [patent_app_country] => US [patent_app_date] => 2005-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011406.pdf [firstpage_image] =>[orig_patent_app_number] => 11175504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/175504
Systems and methods for increasing yield of devices having cache memories by inhibiting use of defective cache entries Jul 5, 2005 Issued
Array ( [id] => 321198 [patent_doc_number] => 07523249 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-21 [patent_title] => 'Direct logical block addressing flash memory mass storage architecture' [patent_app_type] => utility [patent_app_number] => 11/165864 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4199 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523249.pdf [firstpage_image] =>[orig_patent_app_number] => 11165864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/165864
Direct logical block addressing flash memory mass storage architecture Jun 23, 2005 Issued
Array ( [id] => 231433 [patent_doc_number] => 07603525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Flash memory management method that is resistant to data corruption by power loss' [patent_app_type] => utility [patent_app_number] => 11/159170 [patent_app_country] => US [patent_app_date] => 2005-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6372 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/603/07603525.pdf [firstpage_image] =>[orig_patent_app_number] => 11159170 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/159170
Flash memory management method that is resistant to data corruption by power loss Jun 22, 2005 Issued
Array ( [id] => 9077420 [patent_doc_number] => 08555013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-08 [patent_title] => 'Method and system for memory protection by processor carrier based access control' [patent_app_type] => utility [patent_app_number] => 11/158774 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4049 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11158774 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/158774
Method and system for memory protection by processor carrier based access control Jun 21, 2005 Issued
Array ( [id] => 5794984 [patent_doc_number] => 20060015665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Method and system for configuring and using virtual pointers to access one or more independent address spaces' [patent_app_type] => utility [patent_app_number] => 11/148978 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 93835 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015665.pdf [firstpage_image] =>[orig_patent_app_number] => 11148978 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/148978
Method and system for configuring and using virtual pointers to access one or more independent address spaces Jun 7, 2005 Issued
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