Search

Eric Chang

Examiner (ID: 18524, Phone: (571)272-3671 , Office: P/2116 )

Most Active Art Unit
2116
Art Unit(s)
2116, 2186, 2185
Total Applications
657
Issued Applications
458
Pending Applications
14
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10873264 [patent_doc_number] => 08898485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Power transfer between devices' [patent_app_type] => utility [patent_app_number] => 12/503605 [patent_app_country] => US [patent_app_date] => 2009-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12503605 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/503605
Power transfer between devices Jul 14, 2009 Issued
Array ( [id] => 9229787 [patent_doc_number] => 08635468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Sleep wake event logging' [patent_app_type] => utility [patent_app_number] => 12/479238 [patent_app_country] => US [patent_app_date] => 2009-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12479238 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479238
Sleep wake event logging Jun 4, 2009 Issued
Array ( [id] => 9834511 [patent_doc_number] => 08943346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-27 [patent_title] => 'Distributed advanced power management' [patent_app_type] => utility [patent_app_number] => 12/455434 [patent_app_country] => US [patent_app_date] => 2009-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3364 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12455434 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/455434
Distributed advanced power management Jun 1, 2009 Issued
Array ( [id] => 6331795 [patent_doc_number] => 20100115316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'METHOD AND SYSTEM FOR MANAGING ENERGY EFFICIENCY OF A NETWORK LINK VIA PLUGGABLE TRANSCEIVER MODULES IN AN ENERGY EFFICIENT NETWORK DEVICE' [patent_app_type] => utility [patent_app_number] => 12/474557 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10201 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20100115316.pdf [firstpage_image] =>[orig_patent_app_number] => 12474557 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/474557
METHOD AND SYSTEM FOR MANAGING ENERGY EFFICIENCY OF A NETWORK LINK VIA PLUGGABLE TRANSCEIVER MODULES IN AN ENERGY EFFICIENT NETWORK DEVICE May 28, 2009 Abandoned
Array ( [id] => 8558138 [patent_doc_number] => 08332623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Embedded electronic device and booting method thereof' [patent_app_type] => utility [patent_app_number] => 12/472755 [patent_app_country] => US [patent_app_date] => 2009-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4223 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12472755 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/472755
Embedded electronic device and booting method thereof May 26, 2009 Issued
Array ( [id] => 6413676 [patent_doc_number] => 20100306518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'METHOD FOR MANAGING THE RESET OF A DATA PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/472737 [patent_app_country] => US [patent_app_date] => 2009-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3606 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306518.pdf [firstpage_image] =>[orig_patent_app_number] => 12472737 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/472737
Method for managing the reset of a data processor May 26, 2009 Issued
Array ( [id] => 12932230 [patent_doc_number] => 09829950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Power management in a virtual machine farm at the local virtual machine platform level by a platform hypervisor extended with farm management server functions [patent_app_type] => utility [patent_app_number] => 12/471825 [patent_app_country] => US [patent_app_date] => 2009-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2351 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12471825 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/471825
Power management in a virtual machine farm at the local virtual machine platform level by a platform hypervisor extended with farm management server functions May 25, 2009 Issued
Array ( [id] => 5540876 [patent_doc_number] => 20090222681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'METHODS OF CLOCK THROTTLING IN AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/467949 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6299 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20090222681.pdf [firstpage_image] =>[orig_patent_app_number] => 12467949 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467949
METHODS OF CLOCK THROTTLING IN AN INTEGRATED CIRCUIT May 17, 2009 Abandoned
Array ( [id] => 8678692 [patent_doc_number] => 08386827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Systems and methods for signal delay and alignment' [patent_app_type] => utility [patent_app_number] => 12/463585 [patent_app_country] => US [patent_app_date] => 2009-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10115 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12463585 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/463585
Systems and methods for signal delay and alignment May 10, 2009 Issued
Array ( [id] => 5486875 [patent_doc_number] => 20090276640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'POWER MANAGEMENT APPARATUS AND SYSTEM USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/423018 [patent_app_country] => US [patent_app_date] => 2009-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2058 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20090276640.pdf [firstpage_image] =>[orig_patent_app_number] => 12423018 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/423018
POWER MANAGEMENT APPARATUS AND SYSTEM USING THE SAME Apr 13, 2009 Abandoned
Array ( [id] => 8667494 [patent_doc_number] => 08380967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Electronic device, power-on method for an electronic device, and program' [patent_app_type] => utility [patent_app_number] => 12/423188 [patent_app_country] => US [patent_app_date] => 2009-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9773 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12423188 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/423188
Electronic device, power-on method for an electronic device, and program Apr 13, 2009 Issued
Array ( [id] => 9847703 [patent_doc_number] => 08949636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Power efficient flow control model for USB asynchronous transfers' [patent_app_type] => utility [patent_app_number] => 12/368126 [patent_app_country] => US [patent_app_date] => 2009-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6513 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12368126 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/368126
Power efficient flow control model for USB asynchronous transfers Feb 8, 2009 Issued
Array ( [id] => 5577206 [patent_doc_number] => 20090144568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'APPARATUS AND METHOD FOR MODULAR DYNAMICALLY POWER MANAGED POWER SUPPLY AND COOLING SYSTEM FOR COMPUTER SYSTEMS, SERVER APPLICATIONS, AND OTHER ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 12/364780 [patent_app_country] => US [patent_app_date] => 2009-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 56904 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144568.pdf [firstpage_image] =>[orig_patent_app_number] => 12364780 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/364780
Apparatus and method for modular dynamically power managed power supply and cooling system for computer systems, server applications, and other electronic devices Feb 2, 2009 Issued
Array ( [id] => 5356433 [patent_doc_number] => 20090187777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'INCREASING WORKLOAD PERFORMANCE OF ONE OR MORE CORES ON MULTIPLE CORE PROCESSORS' [patent_app_type] => utility [patent_app_number] => 12/357635 [patent_app_country] => US [patent_app_date] => 2009-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3743 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187777.pdf [firstpage_image] =>[orig_patent_app_number] => 12357635 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/357635
INCREASING WORKLOAD PERFORMANCE OF ONE OR MORE CORES ON MULTIPLE CORE PROCESSORS Jan 21, 2009 Abandoned
Array ( [id] => 6362824 [patent_doc_number] => 20100332813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'SYSTEM AND METHOD FOR UTILIZING A PROTECTED/HIDDEN REGION OF SEMICONDUCTOR BASED MEMORY/STORAGE' [patent_app_type] => utility [patent_app_number] => 12/347840 [patent_app_country] => US [patent_app_date] => 2008-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8225 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332813.pdf [firstpage_image] =>[orig_patent_app_number] => 12347840 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/347840
System and method for utilizing a protected/hidden region of semiconductor based memory/storage Dec 30, 2008 Issued
Array ( [id] => 7972213 [patent_doc_number] => 07941685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Delay locked loop for an FPGA architecture' [patent_app_type] => utility [patent_app_number] => 12/337201 [patent_app_country] => US [patent_app_date] => 2008-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 5349 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941685.pdf [firstpage_image] =>[orig_patent_app_number] => 12337201 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/337201
Delay locked loop for an FPGA architecture Dec 16, 2008 Issued
Array ( [id] => 5548132 [patent_doc_number] => 20090158009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'ELECTRONIC EQUIPMENT AND CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/330888 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158009.pdf [firstpage_image] =>[orig_patent_app_number] => 12330888 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/330888
ELECTRONIC EQUIPMENT AND CONTROL METHOD Dec 8, 2008 Abandoned
Array ( [id] => 8667498 [patent_doc_number] => 08380971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Information handling systems including network adapters and methods of booting the information handling systems using boot configuration information from remote sources' [patent_app_type] => utility [patent_app_number] => 12/326588 [patent_app_country] => US [patent_app_date] => 2008-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6343 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12326588 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/326588
Information handling systems including network adapters and methods of booting the information handling systems using boot configuration information from remote sources Dec 1, 2008 Issued
Array ( [id] => 6253172 [patent_doc_number] => 20100138677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'OPTIMIZATION OF DATA DISTRIBUTION AND POWER CONSUMPTION IN A DATA CENTER' [patent_app_type] => utility [patent_app_number] => 12/325314 [patent_app_country] => US [patent_app_date] => 2008-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20100138677.pdf [firstpage_image] =>[orig_patent_app_number] => 12325314 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/325314
OPTIMIZATION OF DATA DISTRIBUTION AND POWER CONSUMPTION IN A DATA CENTER Nov 30, 2008 Abandoned
Array ( [id] => 6384014 [patent_doc_number] => 20100077191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'INFORMATION PROCESSOR, EXTERNAL MEMORY AND CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/325745 [patent_app_country] => US [patent_app_date] => 2008-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2590 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20100077191.pdf [firstpage_image] =>[orig_patent_app_number] => 12325745 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/325745
INFORMATION PROCESSOR, EXTERNAL MEMORY AND CONTROL METHOD Nov 30, 2008 Abandoned
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