| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 1292206
[patent_doc_number] => 06643793
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-04
[patent_title] => 'Apparatus for transferring and holding data based on a selected clock rate'
[patent_app_type] => B1
[patent_app_number] => 09/520209
[patent_app_country] => US
[patent_app_date] => 2000-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8129
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/643/06643793.pdf
[firstpage_image] =>[orig_patent_app_number] => 09520209
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/520209 | Apparatus for transferring and holding data based on a selected clock rate | Mar 6, 2000 | Issued |
| 09/519546 | PERSONALIZING MULTIMEDIA EQUIPMENT CONFIGURATION AT SERVER VIA WEB-ENABLED DEVICE | Mar 5, 2000 | Abandoned |
Array
(
[id] => 7633039
[patent_doc_number] => 06658581
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-02
[patent_title] => 'Timing adjustment of clock signals in a digital circuit'
[patent_app_type] => B1
[patent_app_number] => 09/519463
[patent_app_country] => US
[patent_app_date] => 2000-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 36
[patent_no_of_words] => 20988
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/658/06658581.pdf
[firstpage_image] =>[orig_patent_app_number] => 09519463
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/519463 | Timing adjustment of clock signals in a digital circuit | Mar 5, 2000 | Issued |
Array
(
[id] => 1210455
[patent_doc_number] => 06718477
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-06
[patent_title] => 'Delay locked loop for an FPGA architecture'
[patent_app_type] => B1
[patent_app_number] => 09/519311
[patent_app_country] => US
[patent_app_date] => 2000-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 5226
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/718/06718477.pdf
[firstpage_image] =>[orig_patent_app_number] => 09519311
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/519311 | Delay locked loop for an FPGA architecture | Mar 5, 2000 | Issued |
Array
(
[id] => 1210417
[patent_doc_number] => 06718465
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-06
[patent_title] => 'Reconfigurable inner product processor architecture implementing square recursive decomposition of partial product matrices'
[patent_app_type] => B1
[patent_app_number] => 09/512380
[patent_app_country] => US
[patent_app_date] => 2000-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 41
[patent_no_of_words] => 5567
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/718/06718465.pdf
[firstpage_image] =>[orig_patent_app_number] => 09512380
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/512380 | Reconfigurable inner product processor architecture implementing square recursive decomposition of partial product matrices | Feb 24, 2000 | Issued |
Array
(
[id] => 1027721
[patent_doc_number] => 06886105
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-26
[patent_title] => 'Method and apparatus for resuming memory operations from a low latency wake-up low power state'
[patent_app_type] => utility
[patent_app_number] => 09/504003
[patent_app_country] => US
[patent_app_date] => 2000-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2470
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/886/06886105.pdf
[firstpage_image] =>[orig_patent_app_number] => 09504003
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/504003 | Method and apparatus for resuming memory operations from a low latency wake-up low power state | Feb 13, 2000 | Issued |
Array
(
[id] => 7601943
[patent_doc_number] => 07237101
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-26
[patent_title] => 'Methods and apparatus for self describing devices'
[patent_app_type] => utility
[patent_app_number] => 09/503067
[patent_app_country] => US
[patent_app_date] => 2000-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2262
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/237/07237101.pdf
[firstpage_image] =>[orig_patent_app_number] => 09503067
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/503067 | Methods and apparatus for self describing devices | Feb 11, 2000 | Issued |
Array
(
[id] => 1214536
[patent_doc_number] => 06715088
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-30
[patent_title] => 'METHOD, APPARATUS AND MEMORY MEDIUM STORING A PROGRAM CONTROLLING POWER CONSUMPTION OF AN ELECTRONIC APPARATUS WHILE CONNECTED TO A NETWORK BY CONSTANTLY SUPPLYING STATUS INFORMATION TO A MANAGEMENT APPARATUS, OVER THE NETWORK'
[patent_app_type] => B1
[patent_app_number] => 09/501718
[patent_app_country] => US
[patent_app_date] => 2000-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 54
[patent_no_of_words] => 13534
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/715/06715088.pdf
[firstpage_image] =>[orig_patent_app_number] => 09501718
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/501718 | METHOD, APPARATUS AND MEMORY MEDIUM STORING A PROGRAM CONTROLLING POWER CONSUMPTION OF AN ELECTRONIC APPARATUS WHILE CONNECTED TO A NETWORK BY CONSTANTLY SUPPLYING STATUS INFORMATION TO A MANAGEMENT APPARATUS, OVER THE NETWORK | Feb 9, 2000 | Issued |
Array
(
[id] => 1236407
[patent_doc_number] => 06694445
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-17
[patent_title] => 'Reliable reading of multiple time elements from real-time clock during update and non-update periods'
[patent_app_type] => B1
[patent_app_number] => 09/480952
[patent_app_country] => US
[patent_app_date] => 2000-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2822
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/694/06694445.pdf
[firstpage_image] =>[orig_patent_app_number] => 09480952
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/480952 | Reliable reading of multiple time elements from real-time clock during update and non-update periods | Jan 10, 2000 | Issued |
Array
(
[id] => 1365546
[patent_doc_number] => 06581158
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-17
[patent_title] => 'Method for the resetting of a microcontroller based upon a level of a supply voltage'
[patent_app_type] => B1
[patent_app_number] => 09/476870
[patent_app_country] => US
[patent_app_date] => 2000-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 10
[patent_no_of_words] => 3755
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/581/06581158.pdf
[firstpage_image] =>[orig_patent_app_number] => 09476870
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/476870 | Method for the resetting of a microcontroller based upon a level of a supply voltage | Jan 2, 2000 | Issued |
Array
(
[id] => 1218239
[patent_doc_number] => 06711673
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-23
[patent_title] => 'Using a model specific register as a base I/O address register for embedded I/O registers in a processor'
[patent_app_type] => B1
[patent_app_number] => 09/477124
[patent_app_country] => US
[patent_app_date] => 2000-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2526
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/711/06711673.pdf
[firstpage_image] =>[orig_patent_app_number] => 09477124
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/477124 | Using a model specific register as a base I/O address register for embedded I/O registers in a processor | Jan 2, 2000 | Issued |
Array
(
[id] => 1365558
[patent_doc_number] => 06581159
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-17
[patent_title] => 'Secure method of updating bios by using a simply authenticated external module to further validate new firmware code'
[patent_app_type] => B1
[patent_app_number] => 09/471943
[patent_app_country] => US
[patent_app_date] => 1999-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2963
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/581/06581159.pdf
[firstpage_image] =>[orig_patent_app_number] => 09471943
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/471943 | Secure method of updating bios by using a simply authenticated external module to further validate new firmware code | Dec 22, 1999 | Issued |
Array
(
[id] => 1225793
[patent_doc_number] => 06704865
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-09
[patent_title] => 'Microprocessor conditional deterministic reset vector method'
[patent_app_type] => B1
[patent_app_number] => 09/470742
[patent_app_country] => US
[patent_app_date] => 1999-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2403
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/704/06704865.pdf
[firstpage_image] =>[orig_patent_app_number] => 09470742
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/470742 | Microprocessor conditional deterministic reset vector method | Dec 22, 1999 | Issued |
Array
(
[id] => 1309021
[patent_doc_number] => 06629240
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'Method for monitoring system boot by searching a temporary buffer for BIOS message'
[patent_app_type] => B1
[patent_app_number] => 09/468099
[patent_app_country] => US
[patent_app_date] => 1999-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2585
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/629/06629240.pdf
[firstpage_image] =>[orig_patent_app_number] => 09468099
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/468099 | Method for monitoring system boot by searching a temporary buffer for BIOS message | Dec 20, 1999 | Issued |
Array
(
[id] => 1183632
[patent_doc_number] => 06751726
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-15
[patent_title] => 'Method and system for loading fonts by caching font-loading information'
[patent_app_type] => B1
[patent_app_number] => 09/461967
[patent_app_country] => US
[patent_app_date] => 1999-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6509
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/751/06751726.pdf
[firstpage_image] =>[orig_patent_app_number] => 09461967
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/461967 | Method and system for loading fonts by caching font-loading information | Dec 14, 1999 | Issued |
Array
(
[id] => 1365623
[patent_doc_number] => 06581163
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-17
[patent_title] => 'Mains loss detection apparatus and method'
[patent_app_type] => B1
[patent_app_number] => 09/457114
[patent_app_country] => US
[patent_app_date] => 1999-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2541
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/581/06581163.pdf
[firstpage_image] =>[orig_patent_app_number] => 09457114
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/457114 | Mains loss detection apparatus and method | Dec 6, 1999 | Issued |
Array
(
[id] => 7629961
[patent_doc_number] => 06636978
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-21
[patent_title] => 'Rescheduling data input and output commands for bus synchronization by using digital latency shift detection'
[patent_app_type] => B1
[patent_app_number] => 09/441798
[patent_app_country] => US
[patent_app_date] => 1999-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 28
[patent_no_of_words] => 6043
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 8
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/636/06636978.pdf
[firstpage_image] =>[orig_patent_app_number] => 09441798
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/441798 | Rescheduling data input and output commands for bus synchronization by using digital latency shift detection | Nov 16, 1999 | Issued |
Array
(
[id] => 1407287
[patent_doc_number] => 06560712
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Bus arbitration in low power system'
[patent_app_type] => B1
[patent_app_number] => 09/440857
[patent_app_country] => US
[patent_app_date] => 1999-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3733
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/560/06560712.pdf
[firstpage_image] =>[orig_patent_app_number] => 09440857
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/440857 | Bus arbitration in low power system | Nov 15, 1999 | Issued |
Array
(
[id] => 1431476
[patent_doc_number] => 06519697
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-11
[patent_title] => 'Method and apparatus for coordinating the configuration of massively parallel systems'
[patent_app_type] => B1
[patent_app_number] => 09/440439
[patent_app_country] => US
[patent_app_date] => 1999-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 33
[patent_no_of_words] => 12410
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/519/06519697.pdf
[firstpage_image] =>[orig_patent_app_number] => 09440439
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/440439 | Method and apparatus for coordinating the configuration of massively parallel systems | Nov 14, 1999 | Issued |
Array
(
[id] => 1366875
[patent_doc_number] => 06584576
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-24
[patent_title] => 'Memory system using complementary delay elements to reduce rambus module timing skew'
[patent_app_type] => B1
[patent_app_number] => 09/439792
[patent_app_country] => US
[patent_app_date] => 1999-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2389
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/584/06584576.pdf
[firstpage_image] =>[orig_patent_app_number] => 09439792
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/439792 | Memory system using complementary delay elements to reduce rambus module timing skew | Nov 11, 1999 | Issued |