Search

Eric Coleman

Examiner (ID: 8960, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2302, 2783
Total Applications
2432
Issued Applications
2127
Pending Applications
100
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19917814 [patent_doc_number] => 12293184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-06 [patent_title] => Illegal address mask method and device for cores of DSP [patent_app_type] => utility [patent_app_number] => 19/002787 [patent_app_country] => US [patent_app_date] => 2024-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1077 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19002787 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/002787
Illegal address mask method and device for cores of DSP Dec 26, 2024 Issued
Array ( [id] => 19878485 [patent_doc_number] => 20250110742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => PROCESSOR, METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING [patent_app_type] => utility [patent_app_number] => 18/979402 [patent_app_country] => US [patent_app_date] => 2024-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18979402 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/979402
Processor, method, device and storage medium for data processing Dec 11, 2024 Issued
Array ( [id] => 19892047 [patent_doc_number] => 20250117359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => DUAL PIPELINE PARALLEL SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/913758 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/913758
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY Oct 10, 2024 Pending
Array ( [id] => 19686559 [patent_doc_number] => 20250005104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => COMPUTATIONAL MEMORY [patent_app_type] => utility [patent_app_number] => 18/830123 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830123 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/830123
COMPUTATIONAL MEMORY Sep 9, 2024 Pending
Array ( [id] => 19660535 [patent_doc_number] => 20240427600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF [patent_app_type] => utility [patent_app_number] => 18/827453 [patent_app_country] => US [patent_app_date] => 2024-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 495 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18827453 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/827453
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF Sep 5, 2024 Pending
Array ( [id] => 19878480 [patent_doc_number] => 20250110737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/827415 [patent_app_country] => US [patent_app_date] => 2024-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18827415 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/827415
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS Sep 5, 2024 Pending
Array ( [id] => 19588704 [patent_doc_number] => 20240386261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => NEURAL NETWORK ARCHITECTURE USING CONVOLUTION ENGINES [patent_app_type] => utility [patent_app_number] => 18/788527 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788527
NEURAL NETWORK ARCHITECTURE USING CONVOLUTION ENGINES Jul 29, 2024 Pending
Array ( [id] => 19802661 [patent_doc_number] => 20250068586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => NPU, SOC AND ELECTRONIC DEVICE FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK [patent_app_type] => utility [patent_app_number] => 18/784455 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784455 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/784455
NPU, SOC AND ELECTRONIC DEVICE FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK Jul 24, 2024 Pending
Array ( [id] => 19573866 [patent_doc_number] => 20240378158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/769705 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769705 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769705
METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS Jul 10, 2024 Pending
Array ( [id] => 19530358 [patent_doc_number] => 20240354260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SORTING VECTOR ELEMENTS USING A COUNT VALUE [patent_app_type] => utility [patent_app_number] => 18/762987 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762987 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762987
SORTING VECTOR ELEMENTS USING A COUNT VALUE Jul 2, 2024 Pending
Array ( [id] => 19660782 [patent_doc_number] => 20240427847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS [patent_app_type] => utility [patent_app_number] => 18/757003 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/757003
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS Jun 26, 2024 Pending
Array ( [id] => 20281685 [patent_doc_number] => 20250306927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => VECTOR MASK BUFFERS IN A VECTOR INSTRUCTION EXECUTION PIPELINE [patent_app_type] => utility [patent_app_number] => 18/749599 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749599 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749599
VECTOR MASK BUFFERS IN A VECTOR INSTRUCTION EXECUTION PIPELINE Jun 19, 2024 Pending
Array ( [id] => 19618004 [patent_doc_number] => 20240403684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => INPUT/OUTPUT SYSTEMS AND METHODS FOR SUPERCONDUCTING DEVICES [patent_app_type] => utility [patent_app_number] => 18/735514 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735514 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735514
Input/output systems and methods for superconducting devices Jun 5, 2024 Issued
Array ( [id] => 19466333 [patent_doc_number] => 20240320003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PROCESSOR AND METHOD FOR ASSIGNING CONFIG ID FOR CORE INCLUDED IN THE SAME [patent_app_type] => utility [patent_app_number] => 18/732492 [patent_app_country] => US [patent_app_date] => 2024-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18732492 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/732492
Processor and method for assigning config ID for core included in the same Jun 2, 2024 Issued
Array ( [id] => 19617364 [patent_doc_number] => 20240403044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC [patent_app_type] => utility [patent_app_number] => 18/677140 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677140
NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC May 28, 2024 Pending
Array ( [id] => 19451029 [patent_doc_number] => 20240311159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => Reducing Overhead In Processor Array Searching [patent_app_type] => utility [patent_app_number] => 18/670932 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/670932
Reducing Overhead In Processor Array Searching May 21, 2024 Pending
Array ( [id] => 20070651 [patent_doc_number] => 20250208873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => HIGH LEVEL GRAPH COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/663946 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663946
HIGH LEVEL GRAPH COMPUTING SYSTEM May 13, 2024 Pending
Array ( [id] => 20351468 [patent_doc_number] => 20250348320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => COMPUTING DEVICES WITH INSTRUCTION QUEUES AND PROCESSING-ELEMENT ARRAY CONTROLLERS [patent_app_type] => utility [patent_app_number] => 18/661145 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661145 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661145
COMPUTING DEVICES WITH INSTRUCTION QUEUES AND PROCESSING-ELEMENT ARRAY CONTROLLERS May 9, 2024 Pending
Array ( [id] => 19603181 [patent_doc_number] => 20240394061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => METHODS AND SYSTEMS FOR DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 18/660683 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660683 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660683
METHODS AND SYSTEMS FOR DATA TRANSFER May 9, 2024 Pending
Array ( [id] => 20388177 [patent_doc_number] => 12487903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Automatic generation of computation kernels for approximating elementary functions [patent_app_type] => utility [patent_app_number] => 18/652846 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5399 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652846
Automatic generation of computation kernels for approximating elementary functions May 1, 2024 Issued
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