Search

Eric Coleman

Examiner (ID: 4195, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2783, 2183, 2302
Total Applications
2409
Issued Applications
2133
Pending Applications
63
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18781182 [patent_doc_number] => 11822925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Intelligent scheduling of coprocessor execution [patent_app_type] => utility [patent_app_number] => 17/201855 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201855 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201855
Intelligent scheduling of coprocessor execution Mar 14, 2021 Issued
Array ( [id] => 17187242 [patent_doc_number] => 20210334127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SYSTEM AND METHOD TO ACCELERATE REDUCE OPERATIONS IN GRAPHICS PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/197304 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197304
System and method to accelerate reduce operations in graphics processor Mar 9, 2021 Issued
Array ( [id] => 17069415 [patent_doc_number] => 20210271631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => COMPUTATIONAL MEMORY WITH COOPERATION AMONG ROWS OF PROCESSING ELEMENTS AND MEMORY THEREOF [patent_app_type] => utility [patent_app_number] => 17/187082 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187082
Computational memory with cooperation among rows of processing elements and memory thereof Feb 25, 2021 Issued
Array ( [id] => 17039227 [patent_doc_number] => 20210255863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => PROCESSING METHOD AND PROCESSING DEVICE WITH MATRIX MULTIPLICATION COMPUTATION [patent_app_type] => utility [patent_app_number] => 17/172258 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172258
Processing method and processing device with matrix multiplication computation Feb 9, 2021 Issued
Array ( [id] => 17157817 [patent_doc_number] => 20210318868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => ARITHMETIC PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 17/166286 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166286 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/166286
Arithmetic processing device Feb 2, 2021 Issued
Array ( [id] => 17751458 [patent_doc_number] => 20220229663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => CONTENT-ADDRESSABLE PROCESSING ENGINE [patent_app_type] => utility [patent_app_number] => 17/149936 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149936 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149936
Content-addressable processing engine Jan 14, 2021 Issued
Array ( [id] => 17737097 [patent_doc_number] => 20220222557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => METHODS AND APPARATUS FOR PARALLEL QUANTUM COMPUTING [patent_app_type] => utility [patent_app_number] => 17/248171 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248171 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248171
Methods and apparatus for parallel quantum computing Jan 11, 2021 Issued
Array ( [id] => 17955220 [patent_doc_number] => 11481327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Streaming engine with flexible streaming engine template supporting differing number of nested loops with corresponding loop counts and loop offsets [patent_app_type] => utility [patent_app_number] => 17/146576 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 21262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17146576 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/146576
Streaming engine with flexible streaming engine template supporting differing number of nested loops with corresponding loop counts and loop offsets Jan 11, 2021 Issued
Array ( [id] => 17817193 [patent_doc_number] => 11422804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Processing-in-memory (PIM) device [patent_app_type] => utility [patent_app_number] => 17/145923 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 35322 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 419 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145923
Processing-in-memory (PIM) device Jan 10, 2021 Issued
Array ( [id] => 17651538 [patent_doc_number] => 11354267 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-07 [patent_title] => Compiler for a command-aware hardware architecture [patent_app_type] => utility [patent_app_number] => 17/145662 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145662
Compiler for a command-aware hardware architecture Jan 10, 2021 Issued
Array ( [id] => 17817192 [patent_doc_number] => 11422803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Processing-in-memory (PIM) device [patent_app_type] => utility [patent_app_number] => 17/145245 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 34168 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145245
Processing-in-memory (PIM) device Jan 7, 2021 Issued
Array ( [id] => 17706795 [patent_doc_number] => 20220206801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/134373 [patent_app_country] => US [patent_app_date] => 2020-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134373
Apparatuses, methods, and systems for 8-bit floating-point matrix dot product instructions Dec 25, 2020 Issued
Array ( [id] => 18174119 [patent_doc_number] => 11573829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Task processing method and apparatus, terminal, and computer readable storage medium [patent_app_type] => utility [patent_app_number] => 17/128729 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 21575 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128729 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128729
Task processing method and apparatus, terminal, and computer readable storage medium Dec 20, 2020 Issued
Array ( [id] => 16729676 [patent_doc_number] => 20210096823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => TRANSPOSE OPERATIONS USING PROCESSING ELEMENT ARRAY [patent_app_type] => utility [patent_app_number] => 17/122136 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122136
Transpose operations using processing element array Dec 14, 2020 Issued
Array ( [id] => 17674909 [patent_doc_number] => 20220188076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => DUAL VECTOR ARITHMETIC LOGIC UNIT [patent_app_type] => utility [patent_app_number] => 17/121354 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121354
Dual vector arithmetic logic unit Dec 13, 2020 Issued
Array ( [id] => 17659189 [patent_doc_number] => 20220179654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => METHOD AND APPARATUS FOR COMPARING PREDICTED LOAD VALUE WITH MASKED LOAD VALUE [patent_app_type] => utility [patent_app_number] => 17/114970 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114970
Method and apparatus for comparing predicated load value with masked load value Dec 7, 2020 Issued
Array ( [id] => 16721966 [patent_doc_number] => 20210089113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/115604 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115604 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115604
Distribution of tasks among asymmetric processing elements Dec 7, 2020 Issued
Array ( [id] => 16714054 [patent_doc_number] => 20210081201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS [patent_app_type] => utility [patent_app_number] => 17/107823 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107823
Utilizing structured sparsity in systolic arrays Nov 29, 2020 Issued
Array ( [id] => 17771616 [patent_doc_number] => 11403561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Architecture to support synchronization between core and inference engine for machine learning [patent_app_type] => utility [patent_app_number] => 17/247102 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4795 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247102
Architecture to support synchronization between core and inference engine for machine learning Nov 29, 2020 Issued
Array ( [id] => 17667234 [patent_doc_number] => 11360934 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-14 [patent_title] => Tensor streaming processor architecture [patent_app_type] => utility [patent_app_number] => 17/105976 [patent_app_country] => US [patent_app_date] => 2020-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11834 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105976 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105976
Tensor streaming processor architecture Nov 26, 2020 Issued
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