Eric Coleman

Array ( [id] => 17106371 [patent_doc_number] => 11126588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => RISC processor having specialized registers [patent_app_type] => utility [patent_app_number] => 16/941499 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 11337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17151242 [patent_doc_number] => 11144319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => Redistribution of architected states for a processor register file [patent_app_type] => utility [patent_app_number] => 16/940433 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17394891 [patent_doc_number] => 11243905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-08 [patent_title] => RISC processor having specialized data path for specialized registers [patent_app_type] => utility [patent_app_number] => 16/941485 [patent_app_country] => US [patent_app_date] => 2020-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8752 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17331388 [patent_doc_number] => 11221851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Method executed by computing device, apparatus, device and computer-readable storage medium [patent_app_type] => utility [patent_app_number] => 16/936676 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 7826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17372105 [patent_doc_number] => 20220027157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => VALIDATING MACHINE-READABLE INSTRUCTIONS USING AN ITERATIVE VALIDATION PROCESS [patent_app_type] => utility [patent_app_number] => 16/937048 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17358646 [patent_doc_number] => 20220019442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => RECONFIGURABLE PROCESSING-IN-MEMORY LOGIC USING LOOK-UP TABLES [patent_app_type] => utility [patent_app_number] => 16/932524 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16584880 [patent_doc_number] => 20210019282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => Packet Transmission Method and Apparatus [patent_app_type] => utility [patent_app_number] => 16/928396 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18539373 [patent_doc_number] => 20230244481 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2023-08-03 [patent_title] => BLOCKCHAIN MICROPROCESSOR AND METHOD [patent_app_type] => utility [patent_app_number] => 17/626111 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18539373 [patent_doc_number] => 20230244481 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2023-08-03 [patent_title] => BLOCKCHAIN MICROPROCESSOR AND METHOD [patent_app_type] => utility [patent_app_number] => 17/626111 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17365041 [patent_doc_number] => 11232062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-25 [patent_title] => Parallelism within a systolic array using multiple accumulate busses [patent_app_type] => utility [patent_app_number] => 16/915783 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 36446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17076833 [patent_doc_number] => 11113233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-07 [patent_title] => Multiple busses in a grouped systolic array [patent_app_type] => utility [patent_app_number] => 16/915828 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 36446 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17542904 [patent_doc_number] => 11308027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => Multiple accumulate busses in a systolic array [patent_app_type] => utility [patent_app_number] => 16/915795 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 36447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17542903 [patent_doc_number] => 11308026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => Multiple busses interleaved in a systolic array [patent_app_type] => utility [patent_app_number] => 16/915777 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 36447 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16915777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17771161 [patent_doc_number] => 11403102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Technology to learn and offload common patterns of memory access and computation [patent_app_type] => utility [patent_app_number] => 16/914293 [patent_app_country] => US [patent_app_date] => 2020-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9950 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16543287 [patent_doc_number] => 20200409702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => CALCULATION ENGINE FOR PERFORMING CALCULATIONS BASED ON DEPENDENCIES IN A SELF-DESCRIBING DATA SYSTEM [patent_app_type] => utility [patent_app_number] => 16/913537 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17288427 [patent_doc_number] => 11204977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs [patent_app_type] => utility [patent_app_number] => 16/913800 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 39 [patent_no_of_words] => 29774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17437957 [patent_doc_number] => 11263291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Systems and methods for combining low-mantissa units to achieve and exceed FP64 emulation of matrix multiplication [patent_app_type] => utility [patent_app_number] => 16/913911 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 15577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17106473 [patent_doc_number] => 11126691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => Apparatus and method for generating a vector of elements with a wrapping constraint [patent_app_type] => utility [patent_app_number] => 16/909147 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 14 [patent_no_of_words] => 12974 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17925052 [patent_doc_number] => 11468306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Storage device with artificial intelligence and storage system including the same [patent_app_type] => utility [patent_app_number] => 16/906209 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 11787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18015516 [patent_doc_number] => 11507814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-22 [patent_title] => Neural network based on total hamming distance [patent_app_type] => utility [patent_app_number] => 16/899806 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 15708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899806 [rel_patent_id] =>[rel_patent_doc_number] =>)