Search

Eric Coleman

Examiner (ID: 7488, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2302, 2183, 2783
Total Applications
2413
Issued Applications
2133
Pending Applications
67
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10112210 [patent_doc_number] => 09147629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Extremely thin package' [patent_app_type] => utility [patent_app_number] => 14/032696 [patent_app_country] => US [patent_app_date] => 2013-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 1695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14032696 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/032696
Extremely thin package Sep 19, 2013 Issued
Array ( [id] => 10845147 [patent_doc_number] => 08872327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/024732 [patent_app_country] => US [patent_app_date] => 2013-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 7780 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 423 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14024732 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/024732
Semiconductor device Sep 11, 2013 Issued
Array ( [id] => 9778630 [patent_doc_number] => 08853838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Lead frame and flip packaging device thereof' [patent_app_type] => utility [patent_app_number] => 14/022877 [patent_app_country] => US [patent_app_date] => 2013-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2964 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14022877 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/022877
Lead frame and flip packaging device thereof Sep 9, 2013 Issued
Array ( [id] => 10015968 [patent_doc_number] => 09058989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Large area thin freestanding nitride layers and their use as circuit layers' [patent_app_type] => utility [patent_app_number] => 14/020894 [patent_app_country] => US [patent_app_date] => 2013-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 61 [patent_no_of_words] => 11833 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14020894 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/020894
Large area thin freestanding nitride layers and their use as circuit layers Sep 7, 2013 Issued
Array ( [id] => 9360519 [patent_doc_number] => 20140070391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'LEAD CARRIER WITH PRINT-FORMED TERMINAL PADS' [patent_app_type] => utility [patent_app_number] => 14/018771 [patent_app_country] => US [patent_app_date] => 2013-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6390 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018771 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/018771
Lead carrier with print-formed terminal pads Sep 4, 2013 Issued
Array ( [id] => 10132015 [patent_doc_number] => 09165856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Coupling assembly of power semiconductor device and PCB and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/018932 [patent_app_country] => US [patent_app_date] => 2013-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2432 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14018932 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/018932
Coupling assembly of power semiconductor device and PCB and method for manufacturing the same Sep 4, 2013 Issued
Array ( [id] => 9360512 [patent_doc_number] => 20140070384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'STACKED SEMICONDUCTOR DEVICE AND PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 14/017410 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15574 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017410 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017410
Stacked semiconductor device and printed circuit board Sep 3, 2013 Issued
Array ( [id] => 9202450 [patent_doc_number] => 20140001627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation' [patent_app_type] => utility [patent_app_number] => 14/017963 [patent_app_country] => US [patent_app_date] => 2013-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5164 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14017963 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/017963
Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation Sep 3, 2013 Issued
Array ( [id] => 10551306 [patent_doc_number] => 09275938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-01 [patent_title] => 'Low profile high temperature double sided flip chip power packaging' [patent_app_type] => utility [patent_app_number] => 14/016728 [patent_app_country] => US [patent_app_date] => 2013-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016728 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016728
Low profile high temperature double sided flip chip power packaging Sep 2, 2013 Issued
Array ( [id] => 11014253 [patent_doc_number] => 20160211206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'MULTILAYER STRUCTURE FOR A SEMICONDUCTOR DEVICE AND A METHOD OF FORMING A MULTILAYER STRUCTURE FOR A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/914775 [patent_app_country] => US [patent_app_date] => 2013-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13404 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14914775 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/914775
Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device Aug 27, 2013 Issued
Array ( [id] => 9335099 [patent_doc_number] => 20140061881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/011270 [patent_app_country] => US [patent_app_date] => 2013-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2866 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14011270 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/011270
Integrated circuit Aug 26, 2013 Issued
Array ( [id] => 10958396 [patent_doc_number] => 20140361421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'LEAD FRAME BASED SEMICONDUCTOR DIE PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/972885 [patent_app_country] => US [patent_app_date] => 2013-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13972885 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/972885
Lead frame based semiconductor die package Aug 20, 2013 Issued
Array ( [id] => 10845136 [patent_doc_number] => 08872316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Manufacturing method of semiconductor device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/968289 [patent_app_country] => US [patent_app_date] => 2013-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 10951 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13968289 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/968289
Manufacturing method of semiconductor device and semiconductor device Aug 14, 2013 Issued
Array ( [id] => 9861950 [patent_doc_number] => 20150041967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'Molded Semiconductor Package with Backside Die Metallization' [patent_app_type] => utility [patent_app_number] => 13/964153 [patent_app_country] => US [patent_app_date] => 2013-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5046 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13964153 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/964153
Molded semiconductor package with backside die metallization Aug 11, 2013 Issued
Array ( [id] => 9303928 [patent_doc_number] => 20140042602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'WIRING BOARD AND METHOD FOR MANUFACTURING WIRING BOARD' [patent_app_type] => utility [patent_app_number] => 13/963246 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963246 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/963246
Wiring board and method for manufacturing wiring board Aug 8, 2013 Issued
Array ( [id] => 9178479 [patent_doc_number] => 20130320464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-05 [patent_title] => 'INTEGRALLY MOLDED DIE AND BEZEL STRUCTURE FOR FINGERPRINT SENSORS AND THE LIKE' [patent_app_type] => utility [patent_app_number] => 13/960405 [patent_app_country] => US [patent_app_date] => 2013-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4516 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13960405 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/960405
Integrally molded die and bezel structure for fingerprint sensors and the like Aug 5, 2013 Issued
Array ( [id] => 9277833 [patent_doc_number] => 20140027801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'SOLID STATE LIGHTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/953438 [patent_app_country] => US [patent_app_date] => 2013-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5637 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13953438 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/953438
Solid state lighting device Jul 28, 2013 Issued
Array ( [id] => 9552930 [patent_doc_number] => 08759982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Deskewed multi-die packages' [patent_app_type] => utility [patent_app_number] => 13/950912 [patent_app_country] => US [patent_app_date] => 2013-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 12344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950912 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/950912
Deskewed multi-die packages Jul 24, 2013 Issued
Array ( [id] => 9323519 [patent_doc_number] => 08658539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Fin profile structure and method of making same' [patent_app_type] => utility [patent_app_number] => 13/942286 [patent_app_country] => US [patent_app_date] => 2013-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 7511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942286 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/942286
Fin profile structure and method of making same Jul 14, 2013 Issued
Array ( [id] => 11810262 [patent_doc_number] => 09714827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Metrology method and apparatus, lithographic system, device manufacturing method and substrate' [patent_app_type] => utility [patent_app_number] => 14/412771 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 11914 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14412771 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/412771
Metrology method and apparatus, lithographic system, device manufacturing method and substrate Jun 16, 2013 Issued
Menu