Search

Eric Coleman

Examiner (ID: 4195, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2783, 2183, 2302
Total Applications
2409
Issued Applications
2133
Pending Applications
63
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16651956 [patent_doc_number] => 10929133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Apparatuses, methods, and systems for element sorting of vectors [patent_app_type] => utility [patent_app_number] => 16/249870 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 20949 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249870 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249870
Apparatuses, methods, and systems for element sorting of vectors Jan 15, 2019 Issued
Array ( [id] => 14379133 [patent_doc_number] => 20190163479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => INDIRECT TARGET TAGGED GEOMETRIC BRANCH PREDICTION USING A SET OF TARGET ADDRESS PATTERN DATA [patent_app_type] => utility [patent_app_number] => 16/247714 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247714 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247714
Indirect target tagged geometric branch prediction using a set of target address pattern data Jan 14, 2019 Issued
Array ( [id] => 14570797 [patent_doc_number] => 20190213005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => NEURAL NETWORK COMPUTE TILE [patent_app_type] => utility [patent_app_number] => 16/239760 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239760 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239760
Neural network compute tile Jan 3, 2019 Issued
Array ( [id] => 16494279 [patent_doc_number] => 10860321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Electronic device and method for processing instruction using the same [patent_app_type] => utility [patent_app_number] => 16/205297 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8027 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205297 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205297
Electronic device and method for processing instruction using the same Nov 29, 2018 Issued
Array ( [id] => 16706428 [patent_doc_number] => 10956361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Processor core design optimized for machine learning applications [patent_app_type] => utility [patent_app_number] => 16/205211 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205211 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205211
Processor core design optimized for machine learning applications Nov 28, 2018 Issued
Array ( [id] => 16416542 [patent_doc_number] => 10824434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-03 [patent_title] => Dynamically structured single instruction, multiple data (SIMD) instructions [patent_app_type] => utility [patent_app_number] => 16/204991 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 16322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204991 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/204991
Dynamically structured single instruction, multiple data (SIMD) instructions Nov 28, 2018 Issued
Array ( [id] => 14585341 [patent_doc_number] => 20190220279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => SIMULATION OF EXCLUSIVE INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/203886 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203886 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203886
Simulation of exclusive instructions Nov 28, 2018 Issued
Array ( [id] => 14379163 [patent_doc_number] => 20190163494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => PROCESSOR AND PIPELINING METHOD [patent_app_type] => utility [patent_app_number] => 16/201296 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201296 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/201296
Processor and pipelining method Nov 26, 2018 Issued
Array ( [id] => 16706232 [patent_doc_number] => 10956164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Gating updates to branch predictors to reduce pollution from infrequently executed branches [patent_app_type] => utility [patent_app_number] => 16/201132 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7724 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16201132 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/201132
Gating updates to branch predictors to reduce pollution from infrequently executed branches Nov 26, 2018 Issued
Array ( [id] => 15966825 [patent_doc_number] => 20200167164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => LOOP EXIT PREDICTOR [patent_app_type] => utility [patent_app_number] => 16/200491 [patent_app_country] => US [patent_app_date] => 2018-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200491 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/200491
Loop exit predictor Nov 25, 2018 Issued
Array ( [id] => 16363134 [patent_doc_number] => 20200319885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => VECTOR ADD-WITH-CARRY INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/650999 [patent_app_country] => US [patent_app_date] => 2018-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16650999 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/650999
Vector add-with-carry instruction Nov 14, 2018 Issued
Array ( [id] => 18174457 [patent_doc_number] => 11574171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Neural network architecture using convolution engines [patent_app_type] => utility [patent_app_number] => 16/181559 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 17472 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181559
Neural network architecture using convolution engines Nov 5, 2018 Issued
Array ( [id] => 13992051 [patent_doc_number] => 20190065183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/170577 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170577
Vector galois field multiply sum and accumulate instruction Oct 24, 2018 Issued
Array ( [id] => 13992095 [patent_doc_number] => 20190065205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => VARIABLE LENGTH INSTRUCTION PROCESSOR SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 16/153063 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 44402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153063 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/153063
VARIABLE LENGTH INSTRUCTION PROCESSOR SYSTEM AND METHOD Oct 4, 2018 Abandoned
Array ( [id] => 14188941 [patent_doc_number] => 20190114176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/149050 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149050 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/149050
Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions Sep 30, 2018 Issued
Array ( [id] => 16651966 [patent_doc_number] => 10929143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Method and apparatus for efficient matrix alignment in a systolic array [patent_app_type] => utility [patent_app_number] => 16/147506 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 15590 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147506 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147506
Method and apparatus for efficient matrix alignment in a systolic array Sep 27, 2018 Issued
Array ( [id] => 15685259 [patent_doc_number] => 20200097293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => Low Latency Fetch Circuitry for Compute Kernels [patent_app_type] => utility [patent_app_number] => 16/143416 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143416
Low latency fetch circuitry for compute kernels Sep 25, 2018 Issued
Array ( [id] => 14107053 [patent_doc_number] => 20190095202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => Systems, Apparatuses, and Methods for Arithmetic Recurrence [patent_app_type] => utility [patent_app_number] => 16/139393 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139393 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139393
Systems, apparatuses, and methods for arithmetic recurrence Sep 23, 2018 Issued
Array ( [id] => 15685269 [patent_doc_number] => 20200097298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => APPARATUS AND METHOD FOR PROCESSING STRUCTURE OF ARRAYS (SOA) AND ARRAY OF STRUCTURES (AOS) DATA [patent_app_type] => utility [patent_app_number] => 16/140294 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/140294
Apparatus and method for processing structure of arrays (SoA) and array of structures (AoS) data Sep 23, 2018 Issued
Array ( [id] => 13845527 [patent_doc_number] => 20190026248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => GENERAL-PURPOSE PARALLEL COMPUTING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/138590 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138590
General-purpose parallel computing architecture Sep 20, 2018 Issued
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