Search

Eric Coleman

Examiner (ID: 4195, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2783, 2183, 2302
Total Applications
2409
Issued Applications
2133
Pending Applications
63
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20137960 [patent_doc_number] => 20250245004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => SIGNIFICAND SHIFTING IN FLOATING POINT PROCESSING OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/428137 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428137 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428137
Significand shifting in floating point processing operations Jan 30, 2024 Issued
Array ( [id] => 19617366 [patent_doc_number] => 20240403046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => Load/Store Unit for a Tensor Engine and Methods for Loading or Storing a Tensor [patent_app_type] => utility [patent_app_number] => 18/423210 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423210 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423210
Load/store unit for a tensor engine and methods for loading or storing a tensor Jan 24, 2024 Issued
Array ( [id] => 20123200 [patent_doc_number] => 20250238231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => METHOD AND SYSTEM FOR EFFICIENT DATA MOVEMENT IN VECTOR PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/415926 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415926
Method and system for efficient data movement in vector processors Jan 17, 2024 Issued
Array ( [id] => 19267560 [patent_doc_number] => 20240211263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => NEURAL PROCESSOR AND METHOD FOR FETCHING INSTRUCTIONS THEREOF [patent_app_type] => utility [patent_app_number] => 18/415523 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415523
NEURAL PROCESSOR AND METHOD FOR FETCHING INSTRUCTIONS THEREOF Jan 16, 2024 Pending
Array ( [id] => 19189806 [patent_doc_number] => 20240168719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => DUAL VECTOR ARITHMETIC LOGIC UNIT [patent_app_type] => utility [patent_app_number] => 18/414164 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/414164
Dual vector arithmetic logic unit Jan 15, 2024 Issued
Array ( [id] => 20265780 [patent_doc_number] => 12436771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Performing fused shift and logical operations in processor-based devices [patent_app_type] => utility [patent_app_number] => 18/400294 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3136 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400294
Performing fused shift and logical operations in processor-based devices Dec 28, 2023 Issued
Array ( [id] => 19084732 [patent_doc_number] => 20240111533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR TILE CONFIGURATION [patent_app_type] => utility [patent_app_number] => 18/534012 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534012 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534012
Systems, methods, and apparatus for tile configuration Dec 7, 2023 Issued
Array ( [id] => 19283783 [patent_doc_number] => 20240220259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DATA COMPRESSION USING INSTRUCTION SET ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/525083 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/525083
Data compression using instruction set architecture Nov 29, 2023 Issued
Array ( [id] => 19228301 [patent_doc_number] => 12007937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-11 [patent_title] => Multi-mode architecture for unifying matrix multiplication, 1x1 convolution and 3x3 convolution [patent_app_type] => utility [patent_app_number] => 18/523632 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 17809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523632
Multi-mode architecture for unifying matrix multiplication, 1x1 convolution and 3x3 convolution Nov 28, 2023 Issued
Array ( [id] => 20403604 [patent_doc_number] => 12493577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Digital signal processor (DSP) and electronic device using the same [patent_app_type] => utility [patent_app_number] => 18/512788 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512788 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/512788
Digital signal processor (DSP) and electronic device using the same Nov 16, 2023 Issued
Array ( [id] => 19021941 [patent_doc_number] => 20240078112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => TECHNIQUES FOR DECOUPLED ACCESS-EXECUTE NEAR-MEMORY PROCESSING [patent_app_type] => utility [patent_app_number] => 18/388797 [patent_app_country] => US [patent_app_date] => 2023-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388797 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/388797
Techniques for decoupled access-execute near-memory processing Nov 9, 2023 Issued
Array ( [id] => 20317186 [patent_doc_number] => 12455737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Neural network compute tile [patent_app_type] => utility [patent_app_number] => 18/505743 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4787 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505743
Neural network compute tile Nov 8, 2023 Issued
Array ( [id] => 19251005 [patent_doc_number] => 20240201995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => PROCESSOR AND METHOD FOR ASSIGNING CONFIG ID FOR CORE INCLUDED IN THE SAME [patent_app_type] => utility [patent_app_number] => 18/495645 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18495645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/495645
Processor and method for assigning config ID for core included in the same Oct 25, 2023 Issued
Array ( [id] => 18974008 [patent_doc_number] => 20240054100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => METHOD OF NOTIFYING A PROCESS OR PROGRAMMABLE ATOMIC OPERATION TRAPS [patent_app_type] => utility [patent_app_number] => 18/383311 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18383311 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/383311
Method of notifying a process or programmable atomic operation traps Oct 23, 2023 Issued
Array ( [id] => 19885625 [patent_doc_number] => 12271339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Instruction format and instruction set architecture for tensor streaming processor [patent_app_type] => utility [patent_app_number] => 18/483026 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 131 [patent_no_of_words] => 11858 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483026 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483026
Instruction format and instruction set architecture for tensor streaming processor Oct 8, 2023 Issued
Array ( [id] => 19022041 [patent_doc_number] => 20240078212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => General-Purpose Systolic Array [patent_app_type] => utility [patent_app_number] => 18/376494 [patent_app_country] => US [patent_app_date] => 2023-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376494 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/376494
General-purpose systolic array Oct 3, 2023 Issued
Array ( [id] => 18998153 [patent_doc_number] => 11915001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-27 [patent_title] => Neural processor and method for fetching instructions thereof [patent_app_type] => utility [patent_app_number] => 18/477457 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 22609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/477457
Neural processor and method for fetching instructions thereof Sep 27, 2023 Issued
Array ( [id] => 19956724 [patent_doc_number] => 12327139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Apparatus for accelerating neural networks [patent_app_type] => utility [patent_app_number] => 18/373682 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 3688 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373682 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/373682
Apparatus for accelerating neural networks Sep 26, 2023 Issued
Array ( [id] => 19036379 [patent_doc_number] => 20240086194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => INSTRUCTION AND LOGIC FOR TRACKING FETCH PERFORMANCE BOTTLENECKS [patent_app_type] => utility [patent_app_number] => 18/473088 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18473088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/473088
Instruction and logic for tracking fetch performance bottlenecks Sep 21, 2023 Issued
Array ( [id] => 19114806 [patent_doc_number] => 20240126556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => Vector Instruction Cracking After Scalar Dispatch [patent_app_type] => utility [patent_app_number] => 18/469008 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/469008
Vector instruction cracking after scalar dispatch Sep 17, 2023 Issued
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