
Eric Coleman
Examiner (ID: 7488, Phone: (571)272-4163 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2302, 2183, 2783 |
| Total Applications | 2413 |
| Issued Applications | 2133 |
| Pending Applications | 67 |
| Abandoned Applications | 235 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10831257
[patent_doc_number] => 08859425
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-14
[patent_title] => 'Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs'
[patent_app_type] => utility
[patent_app_number] => 13/652033
[patent_app_country] => US
[patent_app_date] => 2012-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 5115
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13652033
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/652033 | Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs | Oct 14, 2012 | Issued |
Array
(
[id] => 9286866
[patent_doc_number] => 08643197
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-02-04
[patent_title] => 'Encapsulant for a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/651995
[patent_app_country] => US
[patent_app_date] => 2012-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 6142
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13651995
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/651995 | Encapsulant for a semiconductor device | Oct 14, 2012 | Abandoned |
Array
(
[id] => 9418882
[patent_doc_number] => 20140103532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-17
[patent_title] => 'CHIP-LEVEL HUMIDITY PROTECTION'
[patent_app_type] => utility
[patent_app_number] => 13/650872
[patent_app_country] => US
[patent_app_date] => 2012-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7336
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13650872
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/650872 | Chip-level humidity protection | Oct 11, 2012 | Issued |
Array
(
[id] => 9355985
[patent_doc_number] => 08674524
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-03-18
[patent_title] => 'Alignment marks and a semiconductor workpiece'
[patent_app_type] => utility
[patent_app_number] => 13/650197
[patent_app_country] => US
[patent_app_date] => 2012-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 5814
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 6
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13650197
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/650197 | Alignment marks and a semiconductor workpiece | Oct 11, 2012 | Issued |
Array
(
[id] => 9608130
[patent_doc_number] => 08785297
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-22
[patent_title] => 'Method for encapsulating electronic components on a wafer'
[patent_app_type] => utility
[patent_app_number] => 13/649797
[patent_app_country] => US
[patent_app_date] => 2012-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13649797
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/649797 | Method for encapsulating electronic components on a wafer | Oct 10, 2012 | Issued |
Array
(
[id] => 9455765
[patent_doc_number] => 08716777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-06
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/649890
[patent_app_country] => US
[patent_app_date] => 2012-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13649890
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/649890 | Semiconductor device and method for manufacturing the same | Oct 10, 2012 | Issued |
Array
(
[id] => 9355983
[patent_doc_number] => 08674522
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-03-18
[patent_title] => 'Castle-like chop mask for forming staggered datalines for improved contact isolation and pattern thereof'
[patent_app_type] => utility
[patent_app_number] => 13/649125
[patent_app_country] => US
[patent_app_date] => 2012-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2275
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13649125
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/649125 | Castle-like chop mask for forming staggered datalines for improved contact isolation and pattern thereof | Oct 10, 2012 | Issued |
Array
(
[id] => 10832038
[patent_doc_number] => 08860211
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-14
[patent_title] => 'Semiconductor device, semiconductor device manufacturing method, and electronic device'
[patent_app_type] => utility
[patent_app_number] => 13/648397
[patent_app_country] => US
[patent_app_date] => 2012-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
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[patent_no_of_words] => 9922
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13648397
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/648397 | Semiconductor device, semiconductor device manufacturing method, and electronic device | Oct 9, 2012 | Issued |
Array
(
[id] => 9589256
[patent_doc_number] => 08778796
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-15
[patent_title] => 'Multilayer line trimming'
[patent_app_type] => utility
[patent_app_number] => 13/648792
[patent_app_country] => US
[patent_app_date] => 2012-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3218
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13648792
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/648792 | Multilayer line trimming | Oct 9, 2012 | Issued |
Array
(
[id] => 9406286
[patent_doc_number] => 20140097538
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-10
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING A SELF-FORMING BARRIER LAYER AT VIA BOTTOM'
[patent_app_type] => utility
[patent_app_number] => 13/648433
[patent_app_country] => US
[patent_app_date] => 2012-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2940
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13648433
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/648433 | Semiconductor device having a self-forming barrier layer at via bottom | Oct 9, 2012 | Issued |
Array
(
[id] => 9184438
[patent_doc_number] => 08624376
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-01-07
[patent_title] => 'Package-on-package structure without through assembly vias'
[patent_app_type] => utility
[patent_app_number] => 13/649031
[patent_app_country] => US
[patent_app_date] => 2012-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 1959
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13649031
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/649031 | Package-on-package structure without through assembly vias | Oct 9, 2012 | Issued |
Array
(
[id] => 8646657
[patent_doc_number] => 20130032387
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-07
[patent_title] => 'MICROELECTRONIC PACKAGE WITH TERMINALS ON DIELECTRIC MASS'
[patent_app_type] => utility
[patent_app_number] => 13/648495
[patent_app_country] => US
[patent_app_date] => 2012-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13648495
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/648495 | Microelectronic package with terminals on dielectric mass | Oct 9, 2012 | Issued |
Array
(
[id] => 9428264
[patent_doc_number] => 08704344
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-22
[patent_title] => 'Ultra-small chip package and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/647180
[patent_app_country] => US
[patent_app_date] => 2012-10-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/647180 | Ultra-small chip package and method for manufacturing the same | Oct 7, 2012 | Issued |
Array
(
[id] => 9406283
[patent_doc_number] => 20140097535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-10
[patent_title] => 'STACKED MULTI-CHIP INTEGRATED CIRCUIT PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 13/647375
[patent_app_country] => US
[patent_app_date] => 2012-10-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/647375 | Stacked multi-chip integrated circuit package | Oct 7, 2012 | Issued |
Array
(
[id] => 9127816
[patent_doc_number] => 08575767
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-11-05
[patent_title] => 'Reflow of thermoplastic sheet for passivation of power integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 13/646697
[patent_app_country] => US
[patent_app_date] => 2012-10-06
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/646697 | Reflow of thermoplastic sheet for passivation of power integrated circuits | Oct 5, 2012 | Issued |
Array
(
[id] => 8789016
[patent_doc_number] => 20130105985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-02
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/646074 | SEMICONDUCTOR DEVICE | Oct 4, 2012 | Abandoned |
Array
(
[id] => 8812075
[patent_doc_number] => 20130113120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-09
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/646151
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/646151 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE | Oct 4, 2012 | Abandoned |
Array
(
[id] => 10936689
[patent_doc_number] => 20140339710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-20
[patent_title] => 'METHOD FOR BONDING WAFERS AND STRUCTURE OF BONDING PART'
[patent_app_type] => utility
[patent_app_number] => 14/344274
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/344274 | Method for bonding wafers and structure of bonding part | Sep 26, 2012 | Issued |
Array
(
[id] => 10590620
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[patent_issue_date] => 2016-04-12
[patent_title] => 'Dense-pitch small-pad copper wire bonded double IC chip stack packaging piece and preparation method therefor'
[patent_app_type] => utility
[patent_app_number] => 14/363996
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/363996 | Dense-pitch small-pad copper wire bonded double IC chip stack packaging piece and preparation method therefor | Sep 26, 2012 | Issued |
Array
(
[id] => 10851533
[patent_doc_number] => 08878217
[patent_country] => US
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[patent_issue_date] => 2014-11-04
[patent_title] => 'LED package with efficient, isolated thermal path'
[patent_app_type] => utility
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13616759
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/616759 | LED package with efficient, isolated thermal path | Sep 13, 2012 | Issued |