Eric Coleman

Array ( [id] => 16508124 [patent_doc_number] => 20200387380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => APPARATUS AND METHOD FOR MAKING PREDICTIONS FOR BRANCH INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/431881 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16683411 [patent_doc_number] => 10942890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Bit string accumulation in memory array periphery [patent_app_type] => utility [patent_app_number] => 16/430737 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 23561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16683410 [patent_doc_number] => 10942889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Bit string accumulation in memory array periphery [patent_app_type] => utility [patent_app_number] => 16/430689 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 22321 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16470169 [patent_doc_number] => 20200371706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => QUICK CLEARING OF REGISTERS [patent_app_type] => utility [patent_app_number] => 16/422522 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17636787 [patent_doc_number] => 11347511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Floating-point scaling operation [patent_app_type] => utility [patent_app_number] => 16/416453 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 14569 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16470791 [patent_doc_number] => 20200372328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => ACCELERATING NEURON COMPUTATIONS IN ARTIFICIAL NEURAL NETWORKS WITH DUAL SPARSITY [patent_app_type] => utility [patent_app_number] => 16/416891 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16972297 [patent_doc_number] => 11068269 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-20 [patent_title] => Instruction decoding using hash tables [patent_app_type] => utility [patent_app_number] => 16/417033 [patent_app_country] => US [patent_app_date] => 2019-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7243 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14840711 [patent_doc_number] => 20190278756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SORTING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/414301 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16307334 [patent_doc_number] => 10776126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-15 [patent_title] => Flexible hardware engines for handling operating on multidimensional vectors in a video processor [patent_app_type] => utility [patent_app_number] => 16/397476 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14750615 [patent_doc_number] => 20190258481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => INTERRUPTIBLE AND RESTARTABLE MATRIX MULTIPLICATION INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/398200 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16398200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17238278 [patent_doc_number] => 11182157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Information processing device, arithmetic device, and information processing method [patent_app_type] => utility [patent_app_number] => 17/047776 [patent_app_country] => US [patent_app_date] => 2019-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7205 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17047776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16667076 [patent_doc_number] => 10936322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Method for handling exceptions in exception-driven system [patent_app_type] => utility [patent_app_number] => 16/392408 [patent_app_country] => US [patent_app_date] => 2019-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16392408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16856841 [patent_doc_number] => 20210157586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => METHOD SECURED AGAINST SIDE-CHANNEL ATTACKS PERFORMING AN ARITHMETIC OPERATION OF A CRYPTOGRAPHIC ALGORITHM MIXING BOOLEAN AND ARITHMETIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/048262 [patent_app_country] => US [patent_app_date] => 2019-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17048262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16651954 [patent_doc_number] => 10929131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Instruction and logic for processing text strings [patent_app_type] => utility [patent_app_number] => 16/384865 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11630 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14657471 [patent_doc_number] => 20190235864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => GENERATING AND VERIFYING HARDWARE INSTRUCTION TRACES INCLUDING MEMORY DATA CONTENTS [patent_app_type] => utility [patent_app_number] => 16/382740 [patent_app_country] => US [patent_app_date] => 2019-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16363911 [patent_doc_number] => 20200320662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => ACCUMULATOR POOLING MECHANISM [patent_app_type] => utility [patent_app_number] => 16/378047 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14585347 [patent_doc_number] => 20190220282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => Energy Efficient Processor Core Architecture for Image Processor [patent_app_type] => utility [patent_app_number] => 16/368288 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16346870 [patent_doc_number] => 20200311521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => LOOP-BASED EXECUTION FOR EFFICIENT DEEP LEARNING [patent_app_type] => utility [patent_app_number] => 16/365460 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16365460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17955503 [patent_doc_number] => 11481612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Storage of input values across multiple cores of neural network inference circuit [patent_app_type] => utility [patent_app_number] => 16/355656 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 27154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16355656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16371072 [patent_doc_number] => 10802830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Imprecise register dependency tracking [patent_app_type] => utility [patent_app_number] => 16/292933 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9372 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292933 [rel_patent_id] =>[rel_patent_doc_number] =>)