Search

Eric Coleman

Examiner (ID: 4195, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2783, 2183, 2302
Total Applications
2409
Issued Applications
2133
Pending Applications
63
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16171644 [patent_doc_number] => 10713214 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-14 [patent_title] => Hardware accelerator for outer-product matrix multiplication [patent_app_type] => utility [patent_app_number] => 16/136294 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5477 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16136294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/136294
Hardware accelerator for outer-product matrix multiplication Sep 19, 2018 Issued
Array ( [id] => 16879814 [patent_doc_number] => 11029961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Calculating wait time for batch scheduler jobs [patent_app_type] => utility [patent_app_number] => 16/133604 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6447 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16133604 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/133604
Calculating wait time for batch scheduler jobs Sep 16, 2018 Issued
Array ( [id] => 15622621 [patent_doc_number] => 20200081715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => HANDLING MULTIPLE CONTROL FLOW INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/124264 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124264 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/124264
Handling multiple control flow instructions Sep 6, 2018 Issued
Array ( [id] => 16307414 [patent_doc_number] => 10776207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Load exploitation and improved pipelineability of hardware instructions [patent_app_type] => utility [patent_app_number] => 16/123761 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 14852 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123761 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/123761
Load exploitation and improved pipelineability of hardware instructions Sep 5, 2018 Issued
Array ( [id] => 14282043 [patent_doc_number] => 20190138306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => Systems, Apparatuses, and Methods for Cumulative Product [patent_app_type] => utility [patent_app_number] => 16/117293 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117293 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117293
Systems, apparatuses, and methods for cumulative product Aug 29, 2018 Issued
Array ( [id] => 13626937 [patent_doc_number] => 20180365020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => GENERATING AND EXECUTING A CONTROL FLOW [patent_app_type] => utility [patent_app_number] => 16/112577 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/112577
Generating and executing a control flow Aug 23, 2018 Issued
Array ( [id] => 16574117 [patent_doc_number] => 10896040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence [patent_app_type] => utility [patent_app_number] => 16/111858 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7263 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111858 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/111858
Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence Aug 23, 2018 Issued
Array ( [id] => 13626919 [patent_doc_number] => 20180365011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => IMPLEMENTING A RECEIVED ADD PROGRAM COUNTER IMMEDIATE SHIFT (ADDPCIS) INSTRUCTION USING A MICRO-CODED OR CRACKED SEQUENCE [patent_app_type] => utility [patent_app_number] => 16/111873 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111873 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/111873
Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence Aug 23, 2018 Issued
Array ( [id] => 17143719 [patent_doc_number] => 20210311732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => HIGH-LEVEL SYNTHESIS MULTIPROCESSOR SYSTEM AND THE LIKE [patent_app_type] => utility [patent_app_number] => 17/269114 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17269114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/269114
High-level synthesis multiprocessor system and the like Aug 21, 2018 Issued
Array ( [id] => 16278816 [patent_doc_number] => 10761847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Linear feedback shift register for a reconfigurable logic unit [patent_app_type] => utility [patent_app_number] => 16/104341 [patent_app_country] => US [patent_app_date] => 2018-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16104341 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/104341
Linear feedback shift register for a reconfigurable logic unit Aug 16, 2018 Issued
Array ( [id] => 14022685 [patent_doc_number] => 20190073336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => ASYMMETRIC PERFORMANCE MULTICORE ARCHITECTURE WITH SAME INSTRUCTION SET ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/103798 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103798 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103798
Asymmetric performance multicore architecture with same instruction set architecture Aug 13, 2018 Issued
Array ( [id] => 16737611 [patent_doc_number] => 10963263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions [patent_app_type] => utility [patent_app_number] => 16/059001 [patent_app_country] => US [patent_app_date] => 2018-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 17182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16059001 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/059001
Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions Aug 7, 2018 Issued
Array ( [id] => 15919419 [patent_doc_number] => 10656948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Processor system and method based on instruction read buffer [patent_app_type] => utility [patent_app_number] => 16/050415 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 62 [patent_no_of_words] => 67586 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050415
Processor system and method based on instruction read buffer Jul 30, 2018 Issued
Array ( [id] => 15982129 [patent_doc_number] => 10671392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Systems, apparatuses, and methods for performing delta decoding on packed data elements [patent_app_type] => utility [patent_app_number] => 16/051316 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 16064 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 553 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051316 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/051316
Systems, apparatuses, and methods for performing delta decoding on packed data elements Jul 30, 2018 Issued
Array ( [id] => 16292087 [patent_doc_number] => 10768937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Using return address predictor to speed up control stack return address verification [patent_app_type] => utility [patent_app_number] => 16/046949 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046949 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046949
Using return address predictor to speed up control stack return address verification Jul 25, 2018 Issued
Array ( [id] => 17824902 [patent_doc_number] => 11429850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Performing consecutive mac operations on a set of data using different kernels in a MAC circuit [patent_app_type] => utility [patent_app_number] => 16/040357 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16040357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/040357
Performing consecutive mac operations on a set of data using different kernels in a MAC circuit Jul 18, 2018 Issued
Array ( [id] => 15090333 [patent_doc_number] => 20190339977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Securing Conditional Speculative Instruction Execution [patent_app_type] => utility [patent_app_number] => 16/028750 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16028750 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/028750
Securing conditional speculative instruction execution Jul 5, 2018 Issued
Array ( [id] => 16045977 [patent_doc_number] => 10684860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => High performance processor system and method based on general purpose units [patent_app_type] => utility [patent_app_number] => 16/029323 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 46 [patent_no_of_words] => 46136 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029323 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029323
High performance processor system and method based on general purpose units Jul 5, 2018 Issued
Array ( [id] => 15757701 [patent_doc_number] => 10620962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Appratus and method for using predicted result values [patent_app_type] => utility [patent_app_number] => 16/025116 [patent_app_country] => US [patent_app_date] => 2018-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9886 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16025116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/025116
Appratus and method for using predicted result values Jul 1, 2018 Issued
Array ( [id] => 17031432 [patent_doc_number] => 11093243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Vector interleaving in a data processing apparatus [patent_app_type] => utility [patent_app_number] => 16/630622 [patent_app_country] => US [patent_app_date] => 2018-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8462 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16630622 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/630622
Vector interleaving in a data processing apparatus Jul 1, 2018 Issued
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