
Eric Coleman
Examiner (ID: 8960)
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183, 2302, 2783 |
| Total Applications | 2432 |
| Issued Applications | 2127 |
| Pending Applications | 100 |
| Abandoned Applications | 234 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13992051
[patent_doc_number] => 20190065183
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-28
[patent_title] => VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE INSTRUCTION
[patent_app_type] => utility
[patent_app_number] => 16/170577
[patent_app_country] => US
[patent_app_date] => 2018-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18015
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170577
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/170577 | Vector galois field multiply sum and accumulate instruction | Oct 24, 2018 | Issued |
Array
(
[id] => 13992095
[patent_doc_number] => 20190065205
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-28
[patent_title] => VARIABLE LENGTH INSTRUCTION PROCESSOR SYSTEM AND METHOD
[patent_app_type] => utility
[patent_app_number] => 16/153063
[patent_app_country] => US
[patent_app_date] => 2018-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 44402
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16153063
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/153063 | VARIABLE LENGTH INSTRUCTION PROCESSOR SYSTEM AND METHOD | Oct 4, 2018 | Abandoned |
Array
(
[id] => 14188941
[patent_doc_number] => 20190114176
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-18
[patent_title] => PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 16/149050
[patent_app_country] => US
[patent_app_date] => 2018-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17233
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149050
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/149050 | Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions | Sep 30, 2018 | Issued |
Array
(
[id] => 16651966
[patent_doc_number] => 10929143
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-23
[patent_title] => Method and apparatus for efficient matrix alignment in a systolic array
[patent_app_type] => utility
[patent_app_number] => 16/147506
[patent_app_country] => US
[patent_app_date] => 2018-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 22
[patent_no_of_words] => 15590
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147506
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/147506 | Method and apparatus for efficient matrix alignment in a systolic array | Sep 27, 2018 | Issued |
Array
(
[id] => 15685259
[patent_doc_number] => 20200097293
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => Low Latency Fetch Circuitry for Compute Kernels
[patent_app_type] => utility
[patent_app_number] => 16/143416
[patent_app_country] => US
[patent_app_date] => 2018-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10908
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143416
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/143416 | Low latency fetch circuitry for compute kernels | Sep 25, 2018 | Issued |
Array
(
[id] => 14107053
[patent_doc_number] => 20190095202
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-28
[patent_title] => Systems, Apparatuses, and Methods for Arithmetic Recurrence
[patent_app_type] => utility
[patent_app_number] => 16/139393
[patent_app_country] => US
[patent_app_date] => 2018-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17320
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139393
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/139393 | Systems, apparatuses, and methods for arithmetic recurrence | Sep 23, 2018 | Issued |
Array
(
[id] => 15685269
[patent_doc_number] => 20200097298
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => APPARATUS AND METHOD FOR PROCESSING STRUCTURE OF ARRAYS (SOA) AND ARRAY OF STRUCTURES (AOS) DATA
[patent_app_type] => utility
[patent_app_number] => 16/140294
[patent_app_country] => US
[patent_app_date] => 2018-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20796
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140294
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/140294 | Apparatus and method for processing structure of arrays (SoA) and array of structures (AoS) data | Sep 23, 2018 | Issued |
Array
(
[id] => 13845527
[patent_doc_number] => 20190026248
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-24
[patent_title] => GENERAL-PURPOSE PARALLEL COMPUTING ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 16/138590
[patent_app_country] => US
[patent_app_date] => 2018-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12683
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138590
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/138590 | General-purpose parallel computing architecture | Sep 20, 2018 | Issued |
Array
(
[id] => 16171644
[patent_doc_number] => 10713214
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-07-14
[patent_title] => Hardware accelerator for outer-product matrix multiplication
[patent_app_type] => utility
[patent_app_number] => 16/136294
[patent_app_country] => US
[patent_app_date] => 2018-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5477
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16136294
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/136294 | Hardware accelerator for outer-product matrix multiplication | Sep 19, 2018 | Issued |
Array
(
[id] => 16879814
[patent_doc_number] => 11029961
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-08
[patent_title] => Calculating wait time for batch scheduler jobs
[patent_app_type] => utility
[patent_app_number] => 16/133604
[patent_app_country] => US
[patent_app_date] => 2018-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6447
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16133604
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/133604 | Calculating wait time for batch scheduler jobs | Sep 16, 2018 | Issued |
Array
(
[id] => 15622621
[patent_doc_number] => 20200081715
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-12
[patent_title] => HANDLING MULTIPLE CONTROL FLOW INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 16/124264
[patent_app_country] => US
[patent_app_date] => 2018-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6147
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124264
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/124264 | Handling multiple control flow instructions | Sep 6, 2018 | Issued |
Array
(
[id] => 16307414
[patent_doc_number] => 10776207
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-15
[patent_title] => Load exploitation and improved pipelineability of hardware instructions
[patent_app_type] => utility
[patent_app_number] => 16/123761
[patent_app_country] => US
[patent_app_date] => 2018-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 14852
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123761
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/123761 | Load exploitation and improved pipelineability of hardware instructions | Sep 5, 2018 | Issued |
Array
(
[id] => 14282043
[patent_doc_number] => 20190138306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => Systems, Apparatuses, and Methods for Cumulative Product
[patent_app_type] => utility
[patent_app_number] => 16/117293
[patent_app_country] => US
[patent_app_date] => 2018-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16515
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117293
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/117293 | Systems, apparatuses, and methods for cumulative product | Aug 29, 2018 | Issued |
Array
(
[id] => 13626919
[patent_doc_number] => 20180365011
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-20
[patent_title] => IMPLEMENTING A RECEIVED ADD PROGRAM COUNTER IMMEDIATE SHIFT (ADDPCIS) INSTRUCTION USING A MICRO-CODED OR CRACKED SEQUENCE
[patent_app_type] => utility
[patent_app_number] => 16/111873
[patent_app_country] => US
[patent_app_date] => 2018-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7266
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111873
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/111873 | Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence | Aug 23, 2018 | Issued |
Array
(
[id] => 13626937
[patent_doc_number] => 20180365020
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-20
[patent_title] => GENERATING AND EXECUTING A CONTROL FLOW
[patent_app_type] => utility
[patent_app_number] => 16/112577
[patent_app_country] => US
[patent_app_date] => 2018-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10401
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112577
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/112577 | Generating and executing a control flow | Aug 23, 2018 | Issued |
Array
(
[id] => 16574117
[patent_doc_number] => 10896040
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-19
[patent_title] => Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence
[patent_app_type] => utility
[patent_app_number] => 16/111858
[patent_app_country] => US
[patent_app_date] => 2018-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 7263
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111858
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/111858 | Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence | Aug 23, 2018 | Issued |
Array
(
[id] => 17143719
[patent_doc_number] => 20210311732
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-07
[patent_title] => HIGH-LEVEL SYNTHESIS MULTIPROCESSOR SYSTEM AND THE LIKE
[patent_app_type] => utility
[patent_app_number] => 17/269114
[patent_app_country] => US
[patent_app_date] => 2018-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8594
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17269114
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/269114 | High-level synthesis multiprocessor system and the like | Aug 21, 2018 | Issued |
Array
(
[id] => 16278816
[patent_doc_number] => 10761847
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-01
[patent_title] => Linear feedback shift register for a reconfigurable logic unit
[patent_app_type] => utility
[patent_app_number] => 16/104341
[patent_app_country] => US
[patent_app_date] => 2018-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7328
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16104341
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/104341 | Linear feedback shift register for a reconfigurable logic unit | Aug 16, 2018 | Issued |
Array
(
[id] => 14022685
[patent_doc_number] => 20190073336
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-07
[patent_title] => ASYMMETRIC PERFORMANCE MULTICORE ARCHITECTURE WITH SAME INSTRUCTION SET ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 16/103798
[patent_app_country] => US
[patent_app_date] => 2018-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3863
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103798
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/103798 | Asymmetric performance multicore architecture with same instruction set architecture | Aug 13, 2018 | Issued |
Array
(
[id] => 16737611
[patent_doc_number] => 10963263
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-30
[patent_title] => Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
[patent_app_type] => utility
[patent_app_number] => 16/059001
[patent_app_country] => US
[patent_app_date] => 2018-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 17182
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16059001
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/059001 | Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions | Aug 7, 2018 | Issued |