Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16208887 [patent_doc_number] => 20200241877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR TILE CONFIGURATION [patent_app_type] => utility [patent_app_number] => 16/487777 [patent_app_country] => US [patent_app_date] => 2017-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16487777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/487777
Systems, methods, and apparatus for tile configuration Jun 30, 2017 Issued
Array ( [id] => 17499363 [patent_doc_number] => 11288069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Systems, methods, and apparatuses for tile store [patent_app_type] => utility [patent_app_number] => 16/487755 [patent_app_country] => US [patent_app_date] => 2017-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 46 [patent_no_of_words] => 19117 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16487755 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/487755
Systems, methods, and apparatuses for tile store Jun 30, 2017 Issued
Array ( [id] => 16224830 [patent_doc_number] => 20200249947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR TILE BROADCAST [patent_app_type] => utility [patent_app_number] => 16/487774 [patent_app_country] => US [patent_app_date] => 2017-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16487774 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/487774
Systems, methods, and apparatuses for tile broadcast Jun 30, 2017 Issued
Array ( [id] => 15090323 [patent_doc_number] => 20190339972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR TILE DIAGONAL [patent_app_type] => utility [patent_app_number] => 16/474483 [patent_app_country] => US [patent_app_date] => 2017-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16474483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/474483
Systems, methods, and apparatuses for tile diagonal Jun 30, 2017 Issued
Array ( [id] => 15743439 [patent_doc_number] => 20200110608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => CONTEXT SAVE WITH VARIABLE SAVE STATE SIZE [patent_app_type] => utility [patent_app_number] => 16/624178 [patent_app_country] => US [patent_app_date] => 2017-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16624178 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/624178
Context save with variable save state size Jun 30, 2017 Issued
Array ( [id] => 11982704 [patent_doc_number] => 20170286859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'QUANTUM PROCESSOR WITH INSTANCE PROGRAMMABLE QUBIT CONNECTIVITY' [patent_app_type] => utility [patent_app_number] => 15/628963 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 21541 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628963
QUANTUM PROCESSOR WITH INSTANCE PROGRAMMABLE QUBIT CONNECTIVITY Jun 20, 2017 Abandoned
Array ( [id] => 15854665 [patent_doc_number] => 10642616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Techniques for metadata processing [patent_app_type] => utility [patent_app_number] => 15/624878 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 100 [patent_no_of_words] => 73920 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624878 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/624878
Techniques for metadata processing Jun 15, 2017 Issued
Array ( [id] => 16535167 [patent_doc_number] => 10877767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Register restoring branch instruction [patent_app_type] => utility [patent_app_number] => 16/306969 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16306969 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/306969
Register restoring branch instruction Jun 14, 2017 Issued
Array ( [id] => 12114238 [patent_doc_number] => 09870231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Age based fast instruction issue' [patent_app_type] => utility [patent_app_number] => 15/617287 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6704 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617287 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617287
Age based fast instruction issue Jun 7, 2017 Issued
Array ( [id] => 11965779 [patent_doc_number] => 20170269932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 15/613701 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613701 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/613701
Vector Galois Field Multiply Sum and Accumulate instruction Jun 4, 2017 Issued
Array ( [id] => 13579871 [patent_doc_number] => 20180341484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => Tensor Processor Instruction Set Architecture [patent_app_type] => utility [patent_app_number] => 15/604301 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604301 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604301
Tensor processor instruction set architecture May 23, 2017 Issued
Array ( [id] => 13579875 [patent_doc_number] => 20180341486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => MULTIFUNCTION VECTOR PROCESSOR CIRCUITS [patent_app_type] => utility [patent_app_number] => 15/603934 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603934 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603934
Multifunction vector processor circuits May 23, 2017 Issued
Array ( [id] => 12986041 [patent_doc_number] => 20170344374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => PROCESSOR WITH EFFICIENT REORDER BUFFER (ROB) MANAGEMENT [patent_app_type] => utility [patent_app_number] => 15/603505 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603505 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603505
PROCESSOR WITH EFFICIENT REORDER BUFFER (ROB) MANAGEMENT May 23, 2017 Abandoned
Array ( [id] => 13579869 [patent_doc_number] => 20180341483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => Tensor Register Files [patent_app_type] => utility [patent_app_number] => 15/604270 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604270 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604270
Tensor register files May 23, 2017 Issued
Array ( [id] => 14457507 [patent_doc_number] => 10324714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Apparatus and method for trimming parameters of analog circuits including centralized programmable ALU array [patent_app_type] => utility [patent_app_number] => 15/603261 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9431 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603261
Apparatus and method for trimming parameters of analog circuits including centralized programmable ALU array May 22, 2017 Issued
Array ( [id] => 13579863 [patent_doc_number] => 20180341480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => GENERATING AND VERIFYING HARDWARE INSTRUCTION TRACES INCLUDING MEMORY DATA CONTENTS [patent_app_type] => utility [patent_app_number] => 15/602618 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15602618 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/602618
Generating and verifying hardware instruction traces including memory data contents May 22, 2017 Issued
Array ( [id] => 14266185 [patent_doc_number] => 10282659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Device for implementing artificial neural network with multiple instruction units [patent_app_type] => utility [patent_app_number] => 15/600807 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6600 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600807 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/600807
Device for implementing artificial neural network with multiple instruction units May 21, 2017 Issued
Array ( [id] => 14427005 [patent_doc_number] => 10318306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-11 [patent_title] => Multidimensional vectors in a coprocessor [patent_app_type] => utility [patent_app_number] => 15/598637 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598637
Multidimensional vectors in a coprocessor May 17, 2017 Issued
Array ( [id] => 11945002 [patent_doc_number] => 20170249153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'Energy Efficient Processor Core Architecture for Image Processor' [patent_app_type] => utility [patent_app_number] => 15/595632 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15595632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/595632
Energy efficient processor core architecture for image processor May 14, 2017 Issued
Array ( [id] => 14952657 [patent_doc_number] => 10437593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Techniques for comprehensively synchronizing execution threads [patent_app_type] => utility [patent_app_number] => 15/499843 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8639 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499843 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/499843
Techniques for comprehensively synchronizing execution threads Apr 26, 2017 Issued
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