Search

Eric Coleman

Examiner (ID: 8960)

Most Active Art Unit
2183
Art Unit(s)
2183, 2302, 2783
Total Applications
2432
Issued Applications
2127
Pending Applications
100
Abandoned Applications
234

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16248331 [patent_doc_number] => 10747691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Memory device, a dual inline memory module, a storage device, an apparatus for storing, a method for storing, a computer program, a machine readable storage, and a machine readable medium [patent_app_type] => utility [patent_app_number] => 15/949095 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6123 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949095 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949095
Memory device, a dual inline memory module, a storage device, an apparatus for storing, a method for storing, a computer program, a machine readable storage, and a machine readable medium Apr 9, 2018 Issued
Array ( [id] => 14935061 [patent_doc_number] => 20190303168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => APPARATUS, METHODS, AND SYSTEMS FOR CONDITIONAL QUEUES IN A CONFIGURABLE SPATIAL ACCELERATOR [patent_app_type] => utility [patent_app_number] => 15/944761 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 91907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944761 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944761
Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator Apr 2, 2018 Issued
Array ( [id] => 13483061 [patent_doc_number] => 20180293073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => CACHE STORING DATA FETCHED BY ADDRESS CALCULATING LOAD INSTRUCTION WITH LABEL USED AS ASSOCIATED NAME FOR CONSUMING INSTRUCTION TO REFER [patent_app_type] => utility [patent_app_number] => 15/944655 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944655
Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer Apr 2, 2018 Issued
Array ( [id] => 15788857 [patent_doc_number] => 10628153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Method and system to provide user-level multithreading [patent_app_type] => utility [patent_app_number] => 15/943611 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11889 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943611
Method and system to provide user-level multithreading Apr 1, 2018 Issued
Array ( [id] => 15730859 [patent_doc_number] => 10613858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Method and system to provide user-level multithreading [patent_app_type] => utility [patent_app_number] => 15/943609 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11898 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943609 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943609
Method and system to provide user-level multithreading Apr 1, 2018 Issued
Array ( [id] => 13797265 [patent_doc_number] => 20190012171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => Read and Write Masks Update Instruction for Vectorization of Recursive Computations Over Independent Data [patent_app_type] => utility [patent_app_number] => 15/943363 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943363 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943363
Read and write masks update instruction for vectorization of recursive computations over independent data Apr 1, 2018 Issued
Array ( [id] => 15820517 [patent_doc_number] => 10635438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Method and system to provide user-level multithreading [patent_app_type] => utility [patent_app_number] => 15/943614 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11903 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943614
Method and system to provide user-level multithreading Apr 1, 2018 Issued
Array ( [id] => 14935051 [patent_doc_number] => 20190303163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => APPARATUS AND METHOD FOR SPECULATIVE CONDITIONAL MOVE OPERATION [patent_app_type] => utility [patent_app_number] => 15/941945 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941945 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941945
Apparatus and method for speculative conditional move operation Mar 29, 2018 Issued
Array ( [id] => 14901347 [patent_doc_number] => 20190294439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => DATA PROCESSING SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/934179 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15934179 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/934179
Data processing systems Mar 22, 2018 Issued
Array ( [id] => 14872413 [patent_doc_number] => 20190286448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => Processor with Hardware Supported Memory Buffer Overflow Detection [patent_app_type] => utility [patent_app_number] => 15/923121 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15923121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/923121
Processor with hardware supported memory buffer overflow detection Mar 15, 2018 Issued
Array ( [id] => 15952757 [patent_doc_number] => 10664286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Enhanced performance for graphical processing unit transactional memory [patent_app_type] => utility [patent_app_number] => 15/920157 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15920157 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/920157
Enhanced performance for graphical processing unit transactional memory Mar 12, 2018 Issued
Array ( [id] => 15820525 [patent_doc_number] => 10635442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Instruction and logic for tracking fetch performance bottlenecks [patent_app_type] => utility [patent_app_number] => 15/918927 [patent_app_country] => US [patent_app_date] => 2018-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 22812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15918927 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/918927
Instruction and logic for tracking fetch performance bottlenecks Mar 11, 2018 Issued
Array ( [id] => 15399051 [patent_doc_number] => 10540182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Processor and instruction code generation device [patent_app_type] => utility [patent_app_number] => 15/915730 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12754 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915730 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/915730
Processor and instruction code generation device Mar 7, 2018 Issued
Array ( [id] => 13418377 [patent_doc_number] => 20180260731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => Quantum Approximate Optimization [patent_app_type] => utility [patent_app_number] => 15/914662 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914662 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914662
Quantum approximate optimization Mar 6, 2018 Issued
Array ( [id] => 16551576 [patent_doc_number] => 10884735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Instruction and logic for predication and implicit destination [patent_app_type] => utility [patent_app_number] => 15/905623 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 31 [patent_no_of_words] => 21772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15905623 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/905623
Instruction and logic for predication and implicit destination Feb 25, 2018 Issued
Array ( [id] => 15609211 [patent_doc_number] => 10585667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Method and system to provide user-level multithreading [patent_app_type] => utility [patent_app_number] => 15/900030 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11881 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900030 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900030
Method and system to provide user-level multithreading Feb 19, 2018 Issued
Array ( [id] => 12868684 [patent_doc_number] => 20180181403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => ISSUING INSTRUCTIONS TO MULTIPLE EXECUTION UNITS [patent_app_type] => utility [patent_app_number] => 15/891094 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15891094 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/891094
Issuing instructions to multiple execution units Feb 6, 2018 Issued
Array ( [id] => 15578405 [patent_doc_number] => 10579585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Synchronization in a multi-tile, multi-chip processing arrangement [patent_app_type] => utility [patent_app_number] => 15/886138 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 26033 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886138 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/886138
Synchronization in a multi-tile, multi-chip processing arrangement Jan 31, 2018 Issued
Array ( [id] => 15789303 [patent_doc_number] => 10628377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Synchronization in a multi-tile processing arrangement [patent_app_type] => utility [patent_app_number] => 15/886185 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 20283 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886185 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/886185
Synchronization in a multi-tile processing arrangement Jan 31, 2018 Issued
Array ( [id] => 14628857 [patent_doc_number] => 20190227796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => HINTS IN A DATA PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 15/876430 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876430
Hints in a data processing apparatus Jan 21, 2018 Issued
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