Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11629526 [patent_doc_number] => 20170139715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING DELTA DECODING ON PACKED DATA ELEMENTS' [patent_app_type] => utility [patent_app_number] => 15/419888 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 16892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419888 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419888
Systems, apparatuses, and methods for performing delta decoding on packed data elements Jan 29, 2017 Issued
Array ( [id] => 12775381 [patent_doc_number] => 20180150295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => METHODS FOR EXECUTING A COMPUTER INSTRUCTION AND APPARATUSES USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/403524 [patent_app_country] => US [patent_app_date] => 2017-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403524 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/403524
Methods for executing a computer instruction and apparatuses using the same Jan 10, 2017 Issued
Array ( [id] => 14555419 [patent_doc_number] => 10346171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structures [patent_app_type] => utility [patent_app_number] => 15/402825 [patent_app_country] => US [patent_app_date] => 2017-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 20037 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15402825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/402825
End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structures Jan 9, 2017 Issued
Array ( [id] => 11951316 [patent_doc_number] => 20170255466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'EVENT-DRIVEN DESIGN SIMULATION' [patent_app_type] => utility [patent_app_number] => 15/400004 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 19952 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400004 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400004
Event-driven design simulation Jan 5, 2017 Issued
Array ( [id] => 13269307 [patent_doc_number] => 10146738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Hardware accelerator architecture for processing very-sparse and hyper-sparse matrix data [patent_app_type] => utility [patent_app_number] => 15/396511 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 52 [patent_no_of_words] => 23924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396511 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396511
Hardware accelerator architecture for processing very-sparse and hyper-sparse matrix data Dec 30, 2016 Issued
Array ( [id] => 12892165 [patent_doc_number] => 20180189230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => PROCESSOR IN NON-VOLATILE STORAGE MEMORY [patent_app_type] => utility [patent_app_number] => 15/395415 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395415 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395415
Processor in non-volatile storage memory Dec 29, 2016 Issued
Array ( [id] => 14856545 [patent_doc_number] => 10416999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Processors, methods, and systems with a configurable spatial accelerator [patent_app_type] => utility [patent_app_number] => 15/396395 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 66 [patent_no_of_words] => 40373 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396395
Processors, methods, and systems with a configurable spatial accelerator Dec 29, 2016 Issued
Array ( [id] => 12891649 [patent_doc_number] => 20180189058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => Systems, Apparatuses, and Methods for Arithmetic Recurrence [patent_app_type] => utility [patent_app_number] => 15/396184 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396184
Systems, apparatuses, and methods for arithmetic recurrence Dec 29, 2016 Issued
Array ( [id] => 14202727 [patent_doc_number] => 10268479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Systems, apparatuses, and methods for broadcast compare addition [patent_app_type] => utility [patent_app_number] => 15/396199 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 20212 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396199 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396199
Systems, apparatuses, and methods for broadcast compare addition Dec 29, 2016 Issued
Array ( [id] => 14034375 [patent_doc_number] => 10228938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Apparatus and method for instruction-based flop accounting [patent_app_type] => utility [patent_app_number] => 15/396345 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 15164 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396345 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396345
Apparatus and method for instruction-based flop accounting Dec 29, 2016 Issued
Array ( [id] => 14034373 [patent_doc_number] => 10228937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Programmable matrix processing engine [patent_app_type] => utility [patent_app_number] => 15/395654 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 14778 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395654 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395654
Programmable matrix processing engine Dec 29, 2016 Issued
Array ( [id] => 12513597 [patent_doc_number] => 10001997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Prioritizing instructions based on type [patent_app_type] => utility [patent_app_number] => 15/387394 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/387394
Prioritizing instructions based on type Dec 20, 2016 Issued
Array ( [id] => 11516268 [patent_doc_number] => 20170083342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'PATTERN BASED BRANCH PREDICTION' [patent_app_type] => utility [patent_app_number] => 15/373510 [patent_app_country] => US [patent_app_date] => 2016-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4168 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15373510 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/373510
Pattern based branch prediction Dec 8, 2016 Issued
Array ( [id] => 11629525 [patent_doc_number] => 20170139714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'CACHE STORING DATA FETCHED BY ADDRESS CALCULATING LOAD INSTRUCTION WITH LABEL USED AS ASSOCIATED NAME FOR CONSUMING INSTRUCTION TO REFER' [patent_app_type] => utility [patent_app_number] => 15/357943 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15068 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357943 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357943
Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer Nov 20, 2016 Issued
Array ( [id] => 13948437 [patent_doc_number] => 10209993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Branch predictor that uses multiple byte offsets in hash of instruction block fetch address and branch pattern to generate conditional branch predictor indexes [patent_app_type] => utility [patent_app_number] => 15/333861 [patent_app_country] => US [patent_app_date] => 2016-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7027 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333861 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/333861
Branch predictor that uses multiple byte offsets in hash of instruction block fetch address and branch pattern to generate conditional branch predictor indexes Oct 24, 2016 Issued
Array ( [id] => 12611769 [patent_doc_number] => 20180095753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => PIPELINED PROCESSOR WITH MULTI-ISSUE MICROCODE UNIT HAVING LOCAL BRANCH DECODER [patent_app_type] => utility [patent_app_number] => 15/332403 [patent_app_country] => US [patent_app_date] => 2016-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15332403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/332403
Pipelined processor with multi-issue microcode unit having local branch decoder Oct 23, 2016 Issued
Array ( [id] => 12393102 [patent_doc_number] => 09965282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Systems, apparatuses, and methods for performing delta encoding on packed data elements [patent_app_type] => utility [patent_app_number] => 15/290958 [patent_app_country] => US [patent_app_date] => 2016-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 15755 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15290958 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/290958
Systems, apparatuses, and methods for performing delta encoding on packed data elements Oct 10, 2016 Issued
Array ( [id] => 11403666 [patent_doc_number] => 20170024204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 15/286794 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15286794 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/286794
Vector Galois field multiply sum and accumulate instruction Oct 5, 2016 Issued
Array ( [id] => 13403535 [patent_doc_number] => 20180253310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => VECTOR LOAD INSTRUCTION [patent_app_type] => utility [patent_app_number] => 15/759914 [patent_app_country] => US [patent_app_date] => 2016-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15759914 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/759914
Vector load instruction Sep 4, 2016 Issued
Array ( [id] => 12207462 [patent_doc_number] => 20180052688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'MEMORY MOVE INSTRUCTION SEQUENCE TARGETING AN ACCELERATOR SWITCHBOARD' [patent_app_type] => utility [patent_app_number] => 15/243650 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 27439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15243650 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/243650
Memory move instruction sequence targeting an accelerator switchboard Aug 21, 2016 Issued
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