Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11938547 [patent_doc_number] => 20170242697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'System and Method for Executing an Instruction to Permute a Mask' [patent_app_type] => utility [patent_app_number] => 15/052801 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15052801 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/052801
System and method for executing an instruction to permute a mask Feb 23, 2016 Issued
Array ( [id] => 12532002 [patent_doc_number] => 10007521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-26 [patent_title] => Banked physical register data flow architecture in out-of-order processors [patent_app_type] => utility [patent_app_number] => 15/051465 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 18688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051465 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/051465
Banked physical register data flow architecture in out-of-order processors Feb 22, 2016 Issued
Array ( [id] => 12513579 [patent_doc_number] => 10001991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Data processing device [patent_app_type] => utility [patent_app_number] => 15/015565 [patent_app_country] => US [patent_app_date] => 2016-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7962 [patent_no_of_claims] => 124 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15015565 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/015565
Data processing device Feb 3, 2016 Issued
Array ( [id] => 12228914 [patent_doc_number] => 09916159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Programmable linear feedback shift register' [patent_app_type] => utility [patent_app_number] => 14/995588 [patent_app_country] => US [patent_app_date] => 2016-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4703 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995588 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995588
Programmable linear feedback shift register Jan 13, 2016 Issued
Array ( [id] => 11716907 [patent_doc_number] => 20170185406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'METHODS AND SYSTEMS FOR MANAGING AN INSTRUCTION SEQUENCE WITH A DIVERGENT CONTROL FLOW IN A SIMT ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/982257 [patent_app_country] => US [patent_app_date] => 2015-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10998 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14982257 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/982257
Methods and systems for managing an instruction sequence with a divergent control flow in a SIMT architecture Dec 28, 2015 Issued
Array ( [id] => 13003849 [patent_doc_number] => 10025593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Generating and executing a control flow [patent_app_type] => utility [patent_app_number] => 14/980024 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980024 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980024
Generating and executing a control flow Dec 27, 2015 Issued
Array ( [id] => 12474855 [patent_doc_number] => 09990203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Hardware accuracy counters for application precision and quality feedback [patent_app_type] => utility [patent_app_number] => 14/981310 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14981310 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/981310
Hardware accuracy counters for application precision and quality feedback Dec 27, 2015 Issued
Array ( [id] => 13003849 [patent_doc_number] => 10025593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Generating and executing a control flow [patent_app_type] => utility [patent_app_number] => 14/980024 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980024 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980024
Generating and executing a control flow Dec 27, 2015 Issued
Array ( [id] => 13003849 [patent_doc_number] => 10025593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Generating and executing a control flow [patent_app_type] => utility [patent_app_number] => 14/980024 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980024 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980024
Generating and executing a control flow Dec 27, 2015 Issued
Array ( [id] => 13003849 [patent_doc_number] => 10025593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Generating and executing a control flow [patent_app_type] => utility [patent_app_number] => 14/980024 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10368 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980024 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980024
Generating and executing a control flow Dec 27, 2015 Issued
Array ( [id] => 11716908 [patent_doc_number] => 20170185407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'Method and apparatus for loop-invariant instruction detection and elimination' [patent_app_type] => utility [patent_app_number] => 14/998295 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8028 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998295 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998295
Method and apparatus for loop-invariant instruction detection and elimination Dec 25, 2015 Issued
Array ( [id] => 12495213 [patent_doc_number] => 09996356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 14/998299 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 7804 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998299 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998299
Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor Dec 25, 2015 Issued
Array ( [id] => 11516251 [patent_doc_number] => 20170083325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'Dynamic generation of null instructions' [patent_app_type] => utility [patent_app_number] => 14/998147 [patent_app_country] => US [patent_app_date] => 2015-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998147 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998147
Dynamic generation of null instructions Dec 22, 2015 Issued
Array ( [id] => 11708844 [patent_doc_number] => 20170177342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Instructions and Logic for Vector Bit Field Compression and Expansion' [patent_app_type] => utility [patent_app_number] => 14/979322 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22491 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979322 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979322
Instructions and logic for vector bit field compression and expansion Dec 21, 2015 Issued
Array ( [id] => 11708866 [patent_doc_number] => 20170177366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'SELECTIVE STORING OF PREVIOUSLY DECODED INSTRUCTIONS OF FREQUENTLY-CALLED INSTRUCTION SEQUENCES IN AN INSTRUCTION SEQUENCE BUFFER TO BE EXECUTED BY A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/977840 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11821 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977840 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977840
Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor Dec 21, 2015 Issued
Array ( [id] => 11708841 [patent_doc_number] => 20170177340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'VECTOR STORE/LOAD INSTRUCTIONS FOR ARRAY OF STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/977782 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13835 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977782 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977782
Vector store/load instructions for array of structures Dec 21, 2015 Issued
Array ( [id] => 11708864 [patent_doc_number] => 20170177363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Instructions and Logic for Load-Indices-and-Gather Operations' [patent_app_type] => utility [patent_app_number] => 14/979231 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 30610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979231 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979231
Instructions and Logic for Load-Indices-and-Gather Operations Dec 21, 2015 Abandoned
Array ( [id] => 11780688 [patent_doc_number] => 09389870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-12 [patent_title] => 'Age based fast instruction issue' [patent_app_type] => utility [patent_app_number] => 14/977962 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6705 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977962 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977962
Age based fast instruction issue Dec 21, 2015 Issued
Array ( [id] => 11708842 [patent_doc_number] => 20170177341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'APPARATUS AND METHOD FOR RETRIEVING ELEMENTS FROM A LINKED STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/979236 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14864 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979236 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979236
Apparatus and method for retrieving elements from a linked structure Dec 21, 2015 Issued
Array ( [id] => 14457535 [patent_doc_number] => 10324728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Lightweight interrupts for condition checking [patent_app_type] => utility [patent_app_number] => 14/972219 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972219 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/972219
Lightweight interrupts for condition checking Dec 16, 2015 Issued
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