Search

Eric Coleman

Examiner (ID: 4195, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2783, 2183, 2302
Total Applications
2409
Issued Applications
2133
Pending Applications
63
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19911857 [patent_doc_number] => 12288068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Instruction simulation device and method thereof [patent_app_type] => utility [patent_app_number] => 18/465189 [patent_app_country] => US [patent_app_date] => 2023-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10604 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18465189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/465189
Instruction simulation device and method thereof Sep 11, 2023 Issued
Array ( [id] => 19005848 [patent_doc_number] => 20240069919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CONTROL SYSTEM AND METHOD OF MACHINE AND HOST COMPUTER [patent_app_type] => utility [patent_app_number] => 18/463961 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18463961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/463961
Control system and method of machine and host computer Sep 7, 2023 Issued
Array ( [id] => 20331612 [patent_doc_number] => 12461889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Intelligent graph execution and orchestration engine for a reconfigurable data processor [patent_app_type] => utility [patent_app_number] => 18/243994 [patent_app_country] => US [patent_app_date] => 2023-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 18336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18243994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/243994
Intelligent graph execution and orchestration engine for a reconfigurable data processor Sep 7, 2023 Issued
Array ( [id] => 19719359 [patent_doc_number] => 12204898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Interruptible and restartable matrix multiplication instructions, processors, methods, and systems [patent_app_type] => utility [patent_app_number] => 18/240287 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 19291 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18240287 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/240287
Interruptible and restartable matrix multiplication instructions, processors, methods, and systems Aug 29, 2023 Issued
Array ( [id] => 19427171 [patent_doc_number] => 12086594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Vector friendly instruction format and execution thereof [patent_app_type] => utility [patent_app_number] => 18/239106 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 78 [patent_no_of_words] => 31681 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/239106
Vector friendly instruction format and execution thereof Aug 27, 2023 Issued
Array ( [id] => 18989837 [patent_doc_number] => 20240061806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => MULTI-CORE PROCESSING AND MEMORY ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 18/239040 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239040 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/239040
Multi-core processing and memory arrangement Aug 27, 2023 Issued
Array ( [id] => 18941738 [patent_doc_number] => 20240036877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => GENERATING AND EXECUTING A CONTROL FLOW [patent_app_type] => utility [patent_app_number] => 18/448079 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448079
Generating and executing a control flow Aug 9, 2023 Issued
Array ( [id] => 18810897 [patent_doc_number] => 20230385233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => MULTIPLE ACCUMULATE BUSSES IN A SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/446357 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446357 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446357
Multiple accumulate busses in a systolic array Aug 7, 2023 Issued
Array ( [id] => 18925553 [patent_doc_number] => 20240028557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => ISSUING INSTRUCTIONS ON A VECTOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/365790 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365790
Issuing instructions on a vector processor Aug 3, 2023 Issued
Array ( [id] => 18788146 [patent_doc_number] => 20230376563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => COMPUTATIONAL MEMORY [patent_app_type] => utility [patent_app_number] => 18/230139 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230139 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230139
Computational memory Aug 2, 2023 Issued
Array ( [id] => 19581267 [patent_doc_number] => 12147380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Computational memory with cooperation among rows of processing elements and memory thereof [patent_app_type] => utility [patent_app_number] => 18/224146 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11580 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224146 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/224146
Computational memory with cooperation among rows of processing elements and memory thereof Jul 19, 2023 Issued
Array ( [id] => 18755940 [patent_doc_number] => 20230359385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => QUICK CLEARING OF REGISTERS [patent_app_type] => utility [patent_app_number] => 18/353181 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353181 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/353181
Quick clearing of registers Jul 16, 2023 Issued
Array ( [id] => 19764604 [patent_doc_number] => 12222894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Compiler operations for tensor streaming processor [patent_app_type] => utility [patent_app_number] => 18/351916 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11899 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351916
Compiler operations for tensor streaming processor Jul 12, 2023 Issued
Array ( [id] => 18741693 [patent_doc_number] => 20230350674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => INTERRUPTIBLE AND RESTARTABLE MATRIX MULTIPLICATION INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/220225 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220225 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220225
Interruptible and restartable matrix multiplication instructions, processors, methods, and systems Jul 9, 2023 Issued
Array ( [id] => 19732873 [patent_doc_number] => 12210871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Model processing method and apparatus [patent_app_type] => utility [patent_app_number] => 18/344367 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 16521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344367 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344367
Model processing method and apparatus Jun 28, 2023 Issued
Array ( [id] => 18997706 [patent_doc_number] => 11914548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-02-27 [patent_title] => Flow model computation system with disconnected graphs [patent_app_type] => utility [patent_app_number] => 18/207432 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17035 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 546 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/207432
Flow model computation system with disconnected graphs Jun 7, 2023 Issued
Array ( [id] => 19514196 [patent_doc_number] => 20240345882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SYSTEMS AND METHODS FOR PROCESSING FUNCTIONS IN COMPUTATIONAL STORAGE [patent_app_type] => utility [patent_app_number] => 18/328693 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328693 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328693
Systems and methods for processing functions in computational storage Jun 1, 2023 Issued
Array ( [id] => 18904634 [patent_doc_number] => 20240020119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => VECTOR PROCESSOR WITH EXTENDED VECTOR REGISTERS [patent_app_type] => utility [patent_app_number] => 18/202928 [patent_app_country] => US [patent_app_date] => 2023-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202928 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202928
Vector processor with extended vector registers May 27, 2023 Issued
Array ( [id] => 18810725 [patent_doc_number] => 20230385061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => COMPUTING ACCELERATOR, DATA PROCESSOR AND ASSOCIATED METHOD [patent_app_type] => utility [patent_app_number] => 18/322416 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322416 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322416
COMPUTING ACCELERATOR, DATA PROCESSOR AND ASSOCIATED METHOD May 22, 2023 Abandoned
Array ( [id] => 18810724 [patent_doc_number] => 20230385060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Determining Distances Between Vectors [patent_app_type] => utility [patent_app_number] => 18/199996 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199996 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/199996
Determining distances between vectors May 21, 2023 Issued
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