Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11672371 [patent_doc_number] => 20170161093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'PERFORMANCE OPTIMIZATION ENGINE FOR PROCESSOR PARAMETER ADJUSTMENT' [patent_app_type] => utility [patent_app_number] => 14/958153 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14958153 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/958153
Performance optimization engine for processor parameter adjustment Dec 2, 2015 Issued
Array ( [id] => 11889593 [patent_doc_number] => 09760153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold' [patent_app_type] => utility [patent_app_number] => 14/934772 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14934772 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/934772
Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold Nov 5, 2015 Issued
Array ( [id] => 10710925 [patent_doc_number] => 20160057072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'OPTIMIZING RESOURCE CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 14/932260 [patent_app_country] => US [patent_app_date] => 2015-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14932260 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/932260
Optimizing resource configurations Nov 3, 2015 Issued
Array ( [id] => 14331185 [patent_doc_number] => 10296612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Sorting system [patent_app_type] => utility [patent_app_number] => 14/869374 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869374 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/869374
Sorting system Sep 28, 2015 Issued
Array ( [id] => 11896718 [patent_doc_number] => 09766650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Microcontroller programmable system on a chip with programmable interconnect' [patent_app_type] => utility [patent_app_number] => 14/866439 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 36 [patent_no_of_words] => 18367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14866439 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/866439
Microcontroller programmable system on a chip with programmable interconnect Sep 24, 2015 Issued
Array ( [id] => 10658411 [patent_doc_number] => 20160004556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'DYNAMIC PREDICTION OF HARDWARE TRANSACTION RESOURCE REQUIREMENTS' [patent_app_type] => utility [patent_app_number] => 14/854149 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 19971 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14854149 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/854149
Dynamic prediction of hardware transaction resource requirements Sep 14, 2015 Issued
Array ( [id] => 10658428 [patent_doc_number] => 20160004572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'METHODS FOR SINGLE-OWNER MULTI-CONSUMER WORK QUEUES FOR REPEATABLE TASKS' [patent_app_type] => utility [patent_app_number] => 14/852116 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14852116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/852116
Methods for single-owner multi-consumer work queues for repeatable tasks Sep 10, 2015 Issued
Array ( [id] => 10493770 [patent_doc_number] => 20150378792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'DEFERRAL INSTRUCTION FOR MANAGING TRANSACTIONAL ABORTS IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS' [patent_app_type] => utility [patent_app_number] => 14/839008 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21191 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14839008 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/839008
Deferral instruction for managing transactional aborts in transactional memory computing environments Aug 27, 2015 Issued
Array ( [id] => 10478207 [patent_doc_number] => 20150363223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'PREDICTING THE LENGTH OF A TRANSACTION' [patent_app_type] => utility [patent_app_number] => 14/837164 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 17292 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837164 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/837164
Predicting the length of a transaction Aug 26, 2015 Issued
Array ( [id] => 12932935 [patent_doc_number] => 09830185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Indicating nearing the completion of a transaction [patent_app_type] => utility [patent_app_number] => 14/831966 [patent_app_country] => US [patent_app_date] => 2015-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 17308 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14831966 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/831966
Indicating nearing the completion of a transaction Aug 20, 2015 Issued
Array ( [id] => 12194569 [patent_doc_number] => 09898297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Issuing instructions to multiple execution units' [patent_app_type] => utility [patent_app_number] => 14/830704 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 51 [patent_no_of_words] => 49711 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830704 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830704
Issuing instructions to multiple execution units Aug 18, 2015 Issued
Array ( [id] => 10651070 [patent_doc_number] => 09367322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-14 [patent_title] => 'Age based fast instruction issue' [patent_app_type] => utility [patent_app_number] => 14/809291 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809291 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/809291
Age based fast instruction issue Jul 26, 2015 Issued
Array ( [id] => 10416846 [patent_doc_number] => 20150301856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'TASK PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/792342 [patent_app_country] => US [patent_app_date] => 2015-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 23217 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792342 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/792342
Task processor Jul 5, 2015 Issued
Array ( [id] => 11830601 [patent_doc_number] => 09727343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Apparatus and method for handling exception events' [patent_app_type] => utility [patent_app_number] => 14/788848 [patent_app_country] => US [patent_app_date] => 2015-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10304 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14788848 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/788848
Apparatus and method for handling exception events Jun 30, 2015 Issued
Array ( [id] => 12291099 [patent_doc_number] => 09934041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Pattern based branch prediction [patent_app_type] => utility [patent_app_number] => 14/789065 [patent_app_country] => US [patent_app_date] => 2015-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14789065 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/789065
Pattern based branch prediction Jun 30, 2015 Issued
Array ( [id] => 13679489 [patent_doc_number] => 20160378481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => INSTRUCTION AND LOGIC FOR ENCODED WORD INSTRUCTION COMPRESSION [patent_app_type] => utility [patent_app_number] => 14/750638 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750638 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750638
Instruction and logic for encoded word instruction compression Jun 24, 2015 Issued
Array ( [id] => 12228916 [patent_doc_number] => 09916161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Instruction and logic for tracking fetch performance bottlenecks' [patent_app_type] => utility [patent_app_number] => 14/750535 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 23204 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750535 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750535
Instruction and logic for tracking fetch performance bottlenecks Jun 24, 2015 Issued
Array ( [id] => 13679471 [patent_doc_number] => 20160378472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => Instruction and Logic for Predication and Implicit Destination [patent_app_type] => utility [patent_app_number] => 14/750940 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750940 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750940
Instruction and logic for predication and implicit destination Jun 24, 2015 Issued
Array ( [id] => 12039409 [patent_doc_number] => 09817642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Apparatus and method for efficient call/return emulation using a dual return stack buffer' [patent_app_type] => utility [patent_app_number] => 14/751052 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 18548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751052 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751052
Apparatus and method for efficient call/return emulation using a dual return stack buffer Jun 24, 2015 Issued
Array ( [id] => 10493712 [patent_doc_number] => 20150378734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SYSTEM AND METHODS FOR EXPANDABLY WIDE OPERAND INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/749955 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14749955 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/749955
System and methods for expandably wide processor instructions Jun 24, 2015 Issued
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