Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13679499 [patent_doc_number] => 20160378486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => METHOD AND APPARATUS FOR EXECUTION MODE SELECTION [patent_app_type] => utility [patent_app_number] => 14/750212 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750212 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750212
Method and apparatus for execution mode selection Jun 24, 2015 Issued
Array ( [id] => 11509122 [patent_doc_number] => 09600282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Endian-mode-independent memory access in a bi-endian-mode processor architecture' [patent_app_type] => utility [patent_app_number] => 14/724995 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8244 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724995 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724995
Endian-mode-independent memory access in a bi-endian-mode processor architecture May 28, 2015 Issued
Array ( [id] => 14523331 [patent_doc_number] => 10338926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Processor with conditional instructions [patent_app_type] => utility [patent_app_number] => 14/716245 [patent_app_country] => US [patent_app_date] => 2015-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6321 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14716245 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/716245
Processor with conditional instructions May 18, 2015 Issued
Array ( [id] => 15982131 [patent_doc_number] => 10671393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Techniques for facilitating cracking and fusion within a same instruction group [patent_app_type] => utility [patent_app_number] => 14/695594 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 19476 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14695594 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/695594
Techniques for facilitating cracking and fusion within a same instruction group Apr 23, 2015 Issued
Array ( [id] => 11117025 [patent_doc_number] => 20160313999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'ENERGY EFFICIENT PROCESSOR CORE ARCHITECTURE FOR IMAGE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/694815 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11012 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694815 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694815
Energy efficient processor core architecture for image processor Apr 22, 2015 Issued
Array ( [id] => 12046329 [patent_doc_number] => 09823932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Branch prediction' [patent_app_type] => utility [patent_app_number] => 14/690603 [patent_app_country] => US [patent_app_date] => 2015-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3347 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14690603 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/690603
Branch prediction Apr 19, 2015 Issued
Array ( [id] => 11273012 [patent_doc_number] => 20160335558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'QUANTUM PROCESSOR WITH INSTANCE PROGRAMMABLE QUBIT CONNECTIVITY' [patent_app_type] => utility [patent_app_number] => 14/691268 [patent_app_country] => US [patent_app_date] => 2015-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 21536 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14691268 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/691268
Quantum processor with instance programmable qubit connectivity Apr 19, 2015 Issued
Array ( [id] => 11889855 [patent_doc_number] => 09760416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Multiprocessor messaging system' [patent_app_type] => utility [patent_app_number] => 14/689735 [patent_app_country] => US [patent_app_date] => 2015-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2692 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14689735 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/689735
Multiprocessor messaging system Apr 16, 2015 Issued
Array ( [id] => 10746068 [patent_doc_number] => 20160092218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'Conditional Stop Instruction with Accurate Dependency Detection' [patent_app_type] => utility [patent_app_number] => 14/688043 [patent_app_country] => US [patent_app_date] => 2015-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14688043 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/688043
Conditional stop instruction with accurate dependency detection Apr 15, 2015 Issued
Array ( [id] => 11095012 [patent_doc_number] => 20160291980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'METHOD AND APPARATUS FOR A SUPERSCALAR PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/676461 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13379 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676461 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676461
Method and apparatus for a self-clocked, event triggered superscalar processor Mar 31, 2015 Issued
Array ( [id] => 11095014 [patent_doc_number] => 20160291982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'PARALLELIZED EXECUTION OF INSTRUCTION SEQUENCES BASED ON PRE-MONITORING' [patent_app_type] => utility [patent_app_number] => 14/673884 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8719 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673884 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673884
Parallelized execution of instruction sequences based on pre-monitoring Mar 30, 2015 Issued
Array ( [id] => 11095011 [patent_doc_number] => 20160291979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'PARALLELIZED EXECUTION OF INSTRUCTION SEQUENCES' [patent_app_type] => utility [patent_app_number] => 14/673889 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8721 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673889 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673889
Parallelized execution of instruction sequences Mar 30, 2015 Issued
Array ( [id] => 11860812 [patent_doc_number] => 09740495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Implementing out of order processor instruction issue queue' [patent_app_type] => utility [patent_app_number] => 14/628188 [patent_app_country] => US [patent_app_date] => 2015-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 5716 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14628188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/628188
Implementing out of order processor instruction issue queue Feb 19, 2015 Issued
Array ( [id] => 11830638 [patent_doc_number] => 09727380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Global register protection in a multi-threaded processor' [patent_app_type] => utility [patent_app_number] => 14/625895 [patent_app_country] => US [patent_app_date] => 2015-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6076 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14625895 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/625895
Global register protection in a multi-threaded processor Feb 18, 2015 Issued
Array ( [id] => 10357207 [patent_doc_number] => 20150242212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'MODELESS INSTRUCTION EXECUTION WITH 64/32-BIT ADDRESSING' [patent_app_type] => utility [patent_app_number] => 14/612090 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7807 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612090 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612090
Modeless instruction execution with 64/32-bit addressing Feb 1, 2015 Issued
Array ( [id] => 12011523 [patent_doc_number] => 09804841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Single instruction multiple data add processors, methods, systems, and instructions' [patent_app_type] => utility [patent_app_number] => 14/600846 [patent_app_country] => US [patent_app_date] => 2015-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 8556 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14600846 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/600846
Single instruction multiple data add processors, methods, systems, and instructions Jan 19, 2015 Issued
Array ( [id] => 14330633 [patent_doc_number] => 10296334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Method and apparatus for performing a vector bit gather [patent_app_type] => utility [patent_app_number] => 14/583639 [patent_app_country] => US [patent_app_date] => 2014-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 15336 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583639 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583639
Method and apparatus for performing a vector bit gather Dec 26, 2014 Issued
Array ( [id] => 10991587 [patent_doc_number] => 20160188532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT SHUFFLE' [patent_app_type] => utility [patent_app_number] => 14/583636 [patent_app_country] => US [patent_app_date] => 2014-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15167 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583636 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583636
Method and apparatus for performing a vector bit shuffle Dec 26, 2014 Issued
Array ( [id] => 10991388 [patent_doc_number] => 20160188333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'METHOD AND APPARATUS FOR COMPRESSING A MASK VALUE' [patent_app_type] => utility [patent_app_number] => 14/583647 [patent_app_country] => US [patent_app_date] => 2014-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15260 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583647 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583647
METHOD AND APPARATUS FOR COMPRESSING A MASK VALUE Dec 26, 2014 Abandoned
Array ( [id] => 10991585 [patent_doc_number] => 20160188530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX AND AN IMMEDIATE' [patent_app_type] => utility [patent_app_number] => 14/583644 [patent_app_country] => US [patent_app_date] => 2014-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15518 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583644 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583644
Method and apparatus for performing a vector permute with an index and an immediate Dec 26, 2014 Issued
Menu