Search

Eric Coleman

Examiner (ID: 7488, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2302, 2183, 2783
Total Applications
2413
Issued Applications
2133
Pending Applications
67
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4557572 [patent_doc_number] => 07821029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Electrostatic protection element' [patent_app_type] => utility [patent_app_number] => 12/542998 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8971 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821029.pdf [firstpage_image] =>[orig_patent_app_number] => 12542998 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/542998
Electrostatic protection element Aug 17, 2009 Issued
Array ( [id] => 5948562 [patent_doc_number] => 20110031624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'MEMS and a Protection Structure Thereof' [patent_app_type] => utility [patent_app_number] => 12/538168 [patent_app_country] => US [patent_app_date] => 2009-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20110031624.pdf [firstpage_image] =>[orig_patent_app_number] => 12538168 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/538168
MEMS and a protection structure thereof Aug 9, 2009 Issued
Array ( [id] => 4462416 [patent_doc_number] => 07880287 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-01 [patent_title] => 'Stud bumps for die alignment' [patent_app_type] => utility [patent_app_number] => 12/537957 [patent_app_country] => US [patent_app_date] => 2009-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3007 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/880/07880287.pdf [firstpage_image] =>[orig_patent_app_number] => 12537957 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/537957
Stud bumps for die alignment Aug 6, 2009 Issued
Array ( [id] => 4446038 [patent_doc_number] => 07863735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-04 [patent_title] => 'Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/538098 [patent_app_country] => US [patent_app_date] => 2009-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 9210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863735.pdf [firstpage_image] =>[orig_patent_app_number] => 12538098 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/538098
Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof Aug 6, 2009 Issued
Array ( [id] => 5490483 [patent_doc_number] => 20090291554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/534885 [patent_app_country] => US [patent_app_date] => 2009-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 40755 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20090291554.pdf [firstpage_image] =>[orig_patent_app_number] => 12534885 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/534885
Semiconductor chip and method for fabricating the same Aug 3, 2009 Issued
Array ( [id] => 9227822 [patent_doc_number] => 08633493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Large area thin freestanding nitride layers and their use as circuit layers' [patent_app_type] => utility [patent_app_number] => 12/462295 [patent_app_country] => US [patent_app_date] => 2009-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 11812 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12462295 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/462295
Large area thin freestanding nitride layers and their use as circuit layers Jul 30, 2009 Issued
Array ( [id] => 8665026 [patent_doc_number] => 08378488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/512265 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3169 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12512265 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512265
Semiconductor device and method of manufacturing the same Jul 29, 2009 Issued
Array ( [id] => 7775620 [patent_doc_number] => 08120166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Semiconductor package and method of manufacturing the same, and semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/512277 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 10007 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120166.pdf [firstpage_image] =>[orig_patent_app_number] => 12512277 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512277
Semiconductor package and method of manufacturing the same, and semiconductor device and method of manufacturing the same Jul 29, 2009 Issued
Array ( [id] => 6247306 [patent_doc_number] => 20100025838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'ELECTRONIC DEVICE PROTECTED AGAINST ELECTRO STATIC DISCHARGE' [patent_app_type] => utility [patent_app_number] => 12/512112 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2397 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20100025838.pdf [firstpage_image] =>[orig_patent_app_number] => 12512112 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512112
Electronic device protected against electro static discharge Jul 29, 2009 Issued
Array ( [id] => 6369050 [patent_doc_number] => 20100314732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'ENHANCED INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/511077 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3570 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0314/20100314732.pdf [firstpage_image] =>[orig_patent_app_number] => 12511077 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/511077
Enhanced integrated circuit package Jul 28, 2009 Issued
Array ( [id] => 4578095 [patent_doc_number] => 07833858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Superjunction trench device formation methods' [patent_app_type] => utility [patent_app_number] => 12/511849 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 9975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/833/07833858.pdf [firstpage_image] =>[orig_patent_app_number] => 12511849 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/511849
Superjunction trench device formation methods Jul 28, 2009 Issued
Array ( [id] => 6145474 [patent_doc_number] => 20110018115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'POP PRECURSOR WITH INTERPOSER FOR TOP PACKAGE BOND PAD PITCH COMPENSATION' [patent_app_type] => utility [patent_app_number] => 12/509012 [patent_app_country] => US [patent_app_date] => 2009-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4384 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20110018115.pdf [firstpage_image] =>[orig_patent_app_number] => 12509012 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/509012
PoP precursor with interposer for top package bond pad pitch compensation Jul 23, 2009 Issued
Array ( [id] => 6145485 [patent_doc_number] => 20110018117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'SEALED JOINT STRUCTURE OF DEVICE AND PROCESS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/508575 [patent_app_country] => US [patent_app_date] => 2009-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4297 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20110018117.pdf [firstpage_image] =>[orig_patent_app_number] => 12508575 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/508575
Sealed joint structure of device and process using the same Jul 23, 2009 Issued
Array ( [id] => 6145501 [patent_doc_number] => 20110018126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'LOW NOISE HIGH THERMAL CONDUCTIVITY MIXED SIGNAL PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/508106 [patent_app_country] => US [patent_app_date] => 2009-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5817 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20110018126.pdf [firstpage_image] =>[orig_patent_app_number] => 12508106 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/508106
Low noise high thermal conductivity mixed signal package Jul 22, 2009 Issued
Array ( [id] => 8578295 [patent_doc_number] => 08344508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Semiconductor device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 12/507386 [patent_app_country] => US [patent_app_date] => 2009-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7391 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12507386 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/507386
Semiconductor device and fabrication method thereof Jul 21, 2009 Issued
Array ( [id] => 6145473 [patent_doc_number] => 20110018114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation' [patent_app_type] => utility [patent_app_number] => 12/507130 [patent_app_country] => US [patent_app_date] => 2009-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5326 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20110018114.pdf [firstpage_image] =>[orig_patent_app_number] => 12507130 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/507130
Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation Jul 21, 2009 Issued
Array ( [id] => 8572287 [patent_doc_number] => 08338937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Flange package for a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/506721 [patent_app_country] => US [patent_app_date] => 2009-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 61 [patent_no_of_words] => 19346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12506721 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/506721
Flange package for a semiconductor device Jul 20, 2009 Issued
Array ( [id] => 5555659 [patent_doc_number] => 20090267236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'Through-Hole Via on Saw Streets' [patent_app_type] => utility [patent_app_number] => 12/496046 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4623 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20090267236.pdf [firstpage_image] =>[orig_patent_app_number] => 12496046 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496046
Through-hole via on saw streets Jun 30, 2009 Issued
Array ( [id] => 6328050 [patent_doc_number] => 20100327430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'SEMICONDUCTOR DEVICE ASSEMBLY HAVING A STRESS-RELIEVING BUFFER LAYER' [patent_app_type] => utility [patent_app_number] => 12/491517 [patent_app_country] => US [patent_app_date] => 2009-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20100327430.pdf [firstpage_image] =>[orig_patent_app_number] => 12491517 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/491517
Semiconductor device assembly having a stress-relieving buffer layer Jun 24, 2009 Issued
Array ( [id] => 8544031 [patent_doc_number] => 08319325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Intra-die routing using back side redistribution layer and associated method' [patent_app_type] => utility [patent_app_number] => 12/483878 [patent_app_country] => US [patent_app_date] => 2009-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3299 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12483878 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/483878
Intra-die routing using back side redistribution layer and associated method Jun 11, 2009 Issued
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