Search

Eric Coleman

Examiner (ID: 10499, Phone: (571)272-4163 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183, 2783, 2302
Total Applications
2406
Issued Applications
2133
Pending Applications
59
Abandoned Applications
235

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10956234 [patent_doc_number] => 20140359255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'Coarse-Grained Data Processor Having Both Global and Direct Interconnects' [patent_app_type] => utility [patent_app_number] => 14/462858 [patent_app_country] => US [patent_app_date] => 2014-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 19136 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14462858 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/462858
Coarse-Grained Data Processor Having Both Global and Direct Interconnects Aug 18, 2014 Abandoned
Array ( [id] => 11006034 [patent_doc_number] => 20160202983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'PROCESSOR SYSTEM AND METHOD BASED ON INSTRUCTION READ BUFFER' [patent_app_type] => utility [patent_app_number] => 14/913341 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 68548 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14913341 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/913341
Processor system and method based on instruction read buffer Aug 17, 2014 Issued
Array ( [id] => 11013202 [patent_doc_number] => 20160210154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'HIGH PERFORMANCE PROCESSOR SYSTEM AND METHOD BASED ON GENERAL PURPOSE UNITS' [patent_app_type] => utility [patent_app_number] => 14/912726 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 46859 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14912726 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/912726
High performance processor system and method based on general purpose units Aug 17, 2014 Issued
Array ( [id] => 11006035 [patent_doc_number] => 20160202985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'Variable Length Instruction Processor System and Method' [patent_app_type] => utility [patent_app_number] => 14/913352 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 46524 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14913352 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/913352
Variable length instruction processor system and method Aug 14, 2014 Issued
Array ( [id] => 11801245 [patent_doc_number] => 09542121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Memory device using extended interface commands' [patent_app_type] => utility [patent_app_number] => 14/459171 [patent_app_country] => US [patent_app_date] => 2014-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459171 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459171
Memory device using extended interface commands Aug 12, 2014 Issued
Array ( [id] => 11359225 [patent_doc_number] => 09535877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Processing system with interspersed processors and communication elements having improved communication routing' [patent_app_type] => utility [patent_app_number] => 14/451900 [patent_app_country] => US [patent_app_date] => 2014-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 21186 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14451900 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/451900
Processing system with interspersed processors and communication elements having improved communication routing Aug 4, 2014 Issued
Array ( [id] => 12101105 [patent_doc_number] => 09858200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Configurable device interfaces' [patent_app_type] => utility [patent_app_number] => 14/450527 [patent_app_country] => US [patent_app_date] => 2014-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 40988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14450527 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/450527
Configurable device interfaces Aug 3, 2014 Issued
Array ( [id] => 16972299 [patent_doc_number] => 11068271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Zero cycle move using free list counts [patent_app_type] => utility [patent_app_number] => 14/444798 [patent_app_country] => US [patent_app_date] => 2014-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14444798 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/444798
Zero cycle move using free list counts Jul 27, 2014 Issued
Array ( [id] => 10221602 [patent_doc_number] => 20150106595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'PRIORITIZING INSTRUCTIONS BASED ON TYPE' [patent_app_type] => utility [patent_app_number] => 14/340932 [patent_app_country] => US [patent_app_date] => 2014-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340932 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340932
Prioritizing instructions based on type Jul 24, 2014 Issued
Array ( [id] => 10177541 [patent_doc_number] => 09207745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold' [patent_app_type] => utility [patent_app_number] => 14/340328 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340328 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/340328
Methods and systems for managing performance and power utilization of a processor employing a fully-multithreaded load threshold Jul 23, 2014 Issued
Array ( [id] => 10603150 [patent_doc_number] => 09323716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Hierarchical reconfigurable computer architecture' [patent_app_type] => utility [patent_app_number] => 14/329226 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8231 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329226 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329226
Hierarchical reconfigurable computer architecture Jul 10, 2014 Issued
Array ( [id] => 11193223 [patent_doc_number] => 09424039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Instruction for implementing vector loops of iterations having an iteration dependent condition' [patent_app_type] => utility [patent_app_number] => 14/327527 [patent_app_country] => US [patent_app_date] => 2014-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 17444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14327527 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/327527
Instruction for implementing vector loops of iterations having an iteration dependent condition Jul 8, 2014 Issued
Array ( [id] => 11791327 [patent_doc_number] => 09400963 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-26 [patent_title] => 'Task prioritization based on users\' interest' [patent_app_type] => utility [patent_app_number] => 14/325478 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5280 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14325478 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/325478
Task prioritization based on users' interest Jul 7, 2014 Issued
Array ( [id] => 9794906 [patent_doc_number] => 20150006850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'PROCESSOR WITH HETEROGENEOUS CLUSTERED ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/314282 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314282 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/314282
PROCESSOR WITH HETEROGENEOUS CLUSTERED ARCHITECTURE Jun 24, 2014 Abandoned
Array ( [id] => 10485541 [patent_doc_number] => 20150370561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'SKIP INSTRUCTION TO SKIP A NUMBER OF INSTRUCTIONS ON A PREDICATE' [patent_app_type] => utility [patent_app_number] => 14/311222 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14311222 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/311222
Skip instruction to skip a number of instructions on a predicate Jun 19, 2014 Issued
Array ( [id] => 10485543 [patent_doc_number] => 20150370562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'EFFICIENT CONDITIONAL INSTRUCTION HAVING COMPANION LOAD PREDICATE BITS INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/311225 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14311225 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/311225
Efficient conditional instruction having companion load predicate bits instruction Jun 19, 2014 Issued
Array ( [id] => 10478188 [patent_doc_number] => 20150363205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'IMPLEMENTING OUT OF ORDER PROCESSOR INSTRUCTION ISSUE QUEUE' [patent_app_type] => utility [patent_app_number] => 14/306328 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 5721 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14306328 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/306328
Implementing out of order processor instruction issue queue Jun 16, 2014 Issued
Array ( [id] => 10907491 [patent_doc_number] => 20140310505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'COMPRESSED INSTRUCTION FORMAT' [patent_app_type] => utility [patent_app_number] => 14/307468 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6590 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14307468 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/307468
Compressed instruction format Jun 16, 2014 Issued
Array ( [id] => 10644288 [patent_doc_number] => 09361160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Virtualization across physical partitions of a multi-core processor (MCP)' [patent_app_type] => utility [patent_app_number] => 14/281062 [patent_app_country] => US [patent_app_date] => 2014-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281062 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/281062
Virtualization across physical partitions of a multi-core processor (MCP) May 18, 2014 Issued
Array ( [id] => 10124188 [patent_doc_number] => 09158547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Methods and apparatus for scalable array processor interrupt detection and response' [patent_app_type] => utility [patent_app_number] => 14/264263 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 13655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264263 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/264263
Methods and apparatus for scalable array processor interrupt detection and response Apr 28, 2014 Issued
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